Method of wafer level chip scale packaging

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S613000

Reexamination Certificate

active

06939789

ABSTRACT:
The invention includes a method of wafer level chip scale packaging including providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end of spaced a distance from the contact pad. Forming an encapsulation layer over the semiconductor device including the redistribution trace. Forming an opening in the encapsulation layer down to the redistribution trace. Forming a contact post in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end. Forming an electrically conductive bump on the semiconductor device and in electrical contact with the contact post.

REFERENCES:
patent: 5219787 (1993-06-01), Carey et al.
patent: 6103552 (2000-08-01), Lin
patent: 6181569 (2001-01-01), Chakravorty
patent: 6566239 (2003-05-01), Makino et al.
patent: 6583040 (2003-06-01), Lin
patent: 2002/0121692 (2002-09-01), Lee et al.

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