Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-03-01
2005-03-01
Kang, Donghee (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S301000, C438S302000, C257S336000, C257S344000, C257S408000
Reexamination Certificate
active
06861318
ABSTRACT:
A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSATand IDLINof the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
REFERENCES:
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5763319 (1998-06-01), Ling et al.
patent: 5841173 (1998-11-01), Yamashita
patent: 5990516 (1999-11-01), Momose et al.
patent: 6239472 (2001-05-01), Shenoy
Kwok K. Ng. “complete guide to semiconductor device”. McGraw-Hill, p. 614.*
Q. Ouyang, et al. “Two-Dimensional Bandgap Engineering in a Novel Si/SiGe pMOSFET With Enhanced Device Performance and Scalability,” IEEE 2000. 0-7803-6279-9/00, pp. 151-154.
M.C. Öztürk, et al. “Ultra-Shallow Source/Drain Junctions for Nanoscale CMOS Using Selective Silicon-Germanium Technology,” Extended Abstracts of International Workshop on Junction Technology 2001, Japan Society of Applied Physics, 2001. ISBN 4-89114-019-4/020-8, pp. 5-1-1 to 5-1-6.
An Steegen, et al. “Silicide induced pattern density and orientation dependent transconductance in MOS transistors,” IEEE 1999. IMEC, Belgium and INSYS, Belgium. 0-7803-5410-9/99, pp. 20.1.1-20.1.4.
Chau Robert S.
Ghani Tahir
Mistry Kaizad R.
Murthy Anand
LandOfFree
Semiconductor transistor having a stressed channel does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor transistor having a stressed channel, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor transistor having a stressed channel will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3448750