Semiconductor device with source line and fabrication method...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S315000

Reexamination Certificate

active

06953965

ABSTRACT:
A semiconductor device comprises a plurality of field-effect transistors and a common source line. Each of the plurality of memory cell transistors includes a semiconductor region of a first conductivity type formed in a semiconductor substrate, a source region and a drain region of a second conductivity type formed in the semiconductor region, an information storage portion capable of electrically writing and erasing data, and at least one control gate electrode including a conductive layer. The common source line is formed on the semiconductor region of the first conductivity type, and electrically connects the source regions of the memory cell transistors. The common source line includes a conductive layer that has a film thickness substantially equal to a film thickness of the conductive layer included in the control gate electrode and is formed of the same material as that of the conductive layer included in the control gate electrode.

REFERENCES:
patent: 6127224 (2000-10-01), Pio
patent: 6160297 (2000-12-01), Shimizu et al.
patent: 6380032 (2002-04-01), Lee et al.
patent: 6411548 (2002-06-01), Sakui et al.
patent: 6703661 (2004-03-01), Wu
patent: 6720579 (2004-04-01), Shin et al.
patent: 2001-223284 (2001-08-01), None
patent: 2001-0081246 (2001-08-01), None
Jung-Dai Choi, et al., “A 0.15 μm NAND Flash Technology with 0.11 μm’Cell Size for 1 Gbit Flash Memory”, 2000 IEEE, IEDM Tech. Dig., (-4- pages).

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