Comparison circuit and method for verification of scan data

Details Comparison circuit and method for verification of scan data Comparison circuit and method for verification of scan data

2005-04-19

2005-04-19

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S732000

Reexamination Certificate

active

06883127

ABSTRACT:
An apparatus and a method are disclosed to save on the integrated circuit die(s) the state of the scan latches coupled to an integrated circuit in a memory unit during an exercise of the integrated circuit by a coupled tester, to compare on the die the saved states to the state of the scan latches in a subsequent exercise of the integrated circuit, and to transmit the result of the comparison to the tester, rather to have to transmit to the tester the scan latch states for a comparison analysis after each exercise of the integrated circuit. The apparatus and method include deriving on the die a signature of the saved scan latch states, and comparing on the die the signature of an exercise of the integrated circuit and subsequently exercise of the integrated circuit. The invention also includes generating on the die a scan latch latching clock for consecutively exercising the integrated circuit without determining off the die, and sending to the die, for each iteration, the latching clock.

REFERENCES:
patent: 4594711 (1986-06-01), Thatte
patent: 5912901 (1999-06-01), Adams et al.
patent: 5930270 (1999-07-01), Forlenza et al.
patent: 6346822 (2002-02-01), Nishikawa
patent: 6560740 (2003-05-01), Zuraski et al.

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