Dynamic semiconductor memory device and bit line precharge...

Details Dynamic semiconductor memory device and bit line precharge... Dynamic semiconductor memory device and bit line precharge...

2005-09-13

2005-09-13

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S222000, C365S229000

Reexamination Certificate

active

06944076

ABSTRACT:
A dynamic semiconductor memory device capable of reducing standby current is disclosed. In a standby mode wherein only a refresh operation is performed, a precharge/equalize signal is activated only during a predetermined period before a word line is activated so as to precharge a bit line pair to a voltage that is half a line voltage immediately before the word line is activated. In the standby mode, the bit line pair is electrically isolated from a regulator that generates a voltage that is half the line voltage except for the above predetermined period, thus preventing leakage current from flowing therebetween even if a defect in which the word line is shorted with the bit lines occurs.

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patent: 5594701 (1997-01-01), Asaka et al.
patent: 6335886 (2002-01-01), Ochi et al.
patent: 5-128858 (1993-05-01), None

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