Method of forming a vertical MOS transistor

Details Method of forming a vertical MOS transistor Method of forming a vertical MOS transistor

2005-09-27

2005-09-27

Blum, David S. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S157000

Reexamination Certificate

active

06949421

ABSTRACT:
A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the first region, and a second (source/drain) region formed in the top surface of the semiconductor region. The distance between the first region and the second region defines the channel length of the transistor.

REFERENCES:
patent: 4750023 (1988-06-01), Shannon
patent: 4871684 (1989-10-01), Glang et al.
patent: 5073519 (1991-12-01), Rodder
patent: 5087581 (1992-02-01), Rodder
patent: 5170243 (1992-12-01), Dhong et al.
patent: 5504359 (1996-04-01), Rodder
patent: 5554869 (1996-09-01), Chang
patent: 5578850 (1996-11-01), Fitch et al.
patent: 5627395 (1997-05-01), Witek et al.
patent: 5825609 (1998-10-01), Andricacos et al.
patent: 5831319 (1998-11-01), Pan
patent: 5894152 (1999-04-01), Jaso et al.
patent: 5912492 (1999-06-01), Chang et al.
patent: 5914851 (1999-06-01), Saenger et al.
patent: 5963800 (1999-10-01), Augusto
patent: 6107125 (2000-08-01), Jaso et al.
patent: 6169017 (2001-01-01), Lee
patent: 6204532 (2001-03-01), Gambino et al.
patent: 6337497 (2002-01-01), Hanafi et al.
patent: 6440801 (2002-08-01), Furukawa et al.
patent: 6504210 (2003-01-01), Divakaruni et al.
patent: 6562681 (2003-05-01), Tuan et al.
patent: 6593614 (2003-07-01), Hofmann et al.
patent: 6642586 (2003-11-01), Takahashi
patent: 6656825 (2003-12-01), Burbach
*Howard Pein and James D. Plummer, “Performance of the 3-D Pencil Flash EPROM Cell and Memory Array”, IEEE Transactions on Electron Devices, vol. 42, No. 11, Nov. 1995, pps. 1982-1991.
*Howard Pein and James D. Plummer, “A 3-D Sidewall Flash EPROM Cell and Memory Array”, Electron Device Letters, vol. 14, No. 8, Aug. 1993, pps. 415-417.

Affiliated with

Also associated with

Rating

Method of forming a vertical MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a vertical MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a vertical MOS transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3430036