Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-18
2005-01-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C324S765010
Reexamination Certificate
active
06845477
ABSTRACT:
A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a test circuit for conducting an operation test on each chip on the test target wafer. Since the test circuit is in a one-to-one relationship with respect to the test target chip, and is arranged on the test wafer other than the test target wafer, the many chips can be simultaneously tested in parallel during the wafer test without increasing an area of the test target chips.
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Hidaka Hideto
Ooishi Tsukasa
De'cady Albert
Kerveros James C.
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