Semiconductor device incorporating a defect controlled...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S412000, C438S483000

Reexamination Certificate

active

06919258

ABSTRACT:
A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening. The second material has a thickness which is less than a critical thickness to maintain the second material in a strained state. The strained second material functions as a channel for charge carriers.

REFERENCES:
patent: 4522662 (1985-06-01), Bradbury et al.
patent: 4557794 (1985-12-01), McGinn et al.
patent: 4619033 (1986-10-01), Jastrzebski
patent: 4755481 (1988-07-01), Faraone
patent: 4760036 (1988-07-01), Schubert
patent: 4891092 (1990-01-01), Jastrzebski
patent: 4952526 (1990-08-01), Pribat et al.
patent: 5120666 (1992-06-01), Gotou
patent: 5202284 (1993-04-01), Kamins et al.
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5445107 (1995-08-01), Roth et al.
patent: 5963817 (1999-10-01), Chu et al.
patent: 6110278 (2000-08-01), Saxena
patent: 6214653 (2001-04-01), Chen et al.
patent: 6228691 (2001-05-01), Doyle
patent: 6261878 (2001-07-01), Doyle et al.
patent: 6326272 (2001-12-01), Chan et al.
patent: 6362071 (2002-03-01), Nguyen et al.
patent: 6392253 (2002-05-01), Saxena
patent: 6429099 (2002-08-01), Christensen et al.
patent: 6492216 (2002-12-01), Yeo et al.
patent: 2002/0123167 (2002-09-01), Fitzgerald
patent: 2002/0123183 (2002-09-01), Fitzgerald
patent: 2002/0125471 (2002-09-01), Fitzgerald et al.
patent: 2002/0125475 (2002-09-01), Chu et al.
patent: 2003/0025131 (2003-02-01), Lee et al.
patent: 2003/0057416 (2003-03-01), Currie et al.
patent: 2003/0057439 (2003-03-01), Fitzgerald
patent: 2004/0135138 (2004-07-01), Hsu et al.
patent: 0 391 081 (1990-03-01), None
patent: WO 03/001671 (2003-01-01), None
patent: WO 03/015142 (2003-02-01), None
Langdo et al., “High Quality Ge on Si by Epitaxial Necking,”Applied Physics Letters, Jun. 19, 2000, vol. 76, No. 25, pp. 3700-3702.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device incorporating a defect controlled... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device incorporating a defect controlled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device incorporating a defect controlled... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3427645

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.