Fabrication process of a trench gate power MOS transistor...

Details Fabrication process of a trench gate power MOS transistor... Fabrication process of a trench gate power MOS transistor...

2005-05-03

2005-05-03

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S589000, C438S751000, C438S757000, C438S723000, C438S138000, C257S238000, C257S302000, C257S331000, C257S329000, C257S341000

Reexamination Certificate

active

06887760

ABSTRACT:
A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized. Source regions are formed by implanting dopants in the body region while using the oxidized edge surfaces as a self-aligned mask, and the implanted dopants are diffused in the body region.

REFERENCES:
patent: 4997783 (1991-03-01), Hsu
patent: 5032888 (1991-07-01), Seki
patent: 6319777 (2001-11-01), Hueting et al.
patent: 6423618 (2002-07-01), Lin et al.
patent: 20010001494 (2001-05-01), Kocon

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