Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-17
2005-05-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S200000, C438S240000, C438S241000, C438S279000
Reexamination Certificate
active
06893927
ABSTRACT:
A method for making a semiconductor device is described. In that method, a metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the sides of the masking layer are lined with a sacrificial layer.
REFERENCES:
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6306715 (2001-10-01), Chan et al.
patent: 6403423 (2002-06-01), Weybright et al.
patent: 6420279 (2002-07-01), Ono et al.
patent: 6432779 (2002-08-01), Hobbs et al.
patent: 6475874 (2002-11-01), Xiang et al.
patent: 6485989 (2002-11-01), Signorini
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6544906 (2003-04-01), Rotondaro et al.
patent: 6617209 (2003-09-01), Chau et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6620713 (2003-09-01), Arghavani et al.
patent: 6689675 (2004-02-01), Parker et al.
patent: 6696327 (2004-02-01), Brask et al.
patent: 6696345 (2004-02-01), Chau et al.
patent: 20020197790 (2002-12-01), Kizilyalli et al.
patent: 20030032303 (2003-02-01), Yu et al.
patent: 20030045080 (2003-03-01), Visokay et al.
patent: 20030180968 (2003-09-01), Nallan et al.
patent: 20030198104 (2003-10-01), Lee
patent: 20040000695 (2004-01-01), Matsuo
patent: 20040023478 (2004-02-01), Samavedam et al.
Polishchuk et al., “Dual Workfuntion CMOS Gate Technology Based on Metal Interdiffusion”, www.eesc.berkeley.edu, 1 page.
Doug Barlage et al., “High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Lu et al., “Dual-Metal Gate Technology for Deep-Submicron CMOS Devices”, dated Apr. 29, 2003, 1 page.
Schwantes et al., “Performance Improvement of Metal Gate CMOS Technologies with Gigabit Feature Sizes”, Technical University of Hanburg-Harburg, 5 pages.
Brask et al., “A Method for Making a Semiconductor Device Having a Metal Gate Electrode,” U.S. Appl. No. 10/704,497, filed Nov. 6, 2003.
Brask et al., “A Method for Etching a Thin Metal Layer”, U.S. Appl. No. 10/704,498, filed Nov. 6, 2003.
Brask et al., “A Method for Making a Semiconductor Device with a Metal Gate Electrode that is Formed on an Annealed High-K Gate Dielectric Layer”, U.S. Appl. No. 10/742,678, filed Dec. 19, 2003.
Brask Justin K.
Chau Robert S.
Doczy Mark L.
Kavalieros Jack
Metz Matthew V.
Anya Igwe U.
Secley Mark V.
Smith Matthew
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