Method of forming a transistor having multiple channels

Details Method of forming a transistor having multiple channels Method of forming a transistor having multiple channels

2005-07-26

2005-07-26

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S284000, C257S331000

Reexamination Certificate

active

06921700

ABSTRACT:
A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.

REFERENCES:
patent: 4859623 (1989-08-01), Busta
patent: 5223724 (1993-06-01), Green, Jr.
patent: 5266506 (1993-11-01), Green, Jr.
patent: 5689127 (1997-11-01), Chu et al.
patent: 6300182 (2001-10-01), Yu
patent: 6365465 (2002-04-01), Chan et al.
patent: 6372559 (2002-04-01), Crowder et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 2002/0185655 (2002-12-01), Fahimulla et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: WO00/21118 (2000-04-01), None
Monfray, S. et al; “50nm-Gate All Around (GAA)-Silicon On Nothing (SON)-Devices; A Simple Way To Co-Integration of GAA Transistors Within Bulk MOSFET Process”; 2002 Technology; Symposium on VLSI Technology; 2002; pp 108-109; 2002 Symposium on VLSI Technology Digest of Technical Papers.
Monfray, S. et al.; “Highly-Performant 38nm SON (Silicon-On-Nothing) P-MOSFETs with 9nm-thick Channels”; 2002 IEEE International SOI Conference; Oct. 2002; pp. 20-22.
Monfray, S. et al.; “ SON (Silicon-On-Nothing) P-MOSFETs with Totally Silicided (CoSi2) Polysilicon on 5nm-thick Si Films: The Simplest Way to Integration of Metal Gates on Thin FD Channels”IEDM; 2002; pp 263-266; IEEE.
Yu, Bin et al; “FinFet Scaling to 10nm Gate Length”; IEDM; 2002; pp 251-254; IEEE.
Kedzierski, Jakub et al.; “High_Performance Symmetric-Gate and CMOS-Compatible V, Asymmetric-Gate FinFET Devices”; IEEE; 2001; 4 pp.
Choi, Y. et al.; “Sub-20nm CMOS FinFET Technologies”; IEDM; 2001; pp. 19.1.1-19.1.4; IEEE.
Kim, K. et al.; “Double-Gate CMOS: Symmetrical-Versus Asymmetrical-Gate Devices”; IEEE Transactions on Electron Devices; Feb., 2001; pp 294-299; vol. 48, No. 2; IEEE.
Monfray, S. et al.; “First 80nm SON (Silicon-On-Nothing) MOSFETs With PErfect Morphology and High Electrical Performance”; IEDM; 2001; pp. 29.7.1-29.7.4; IEEE.
Hisamoto, D. et al.; “FinFET-A-Self-Aligned Double-Gate (MOSFET) Scalable to 20nm”; IEEE Transactions of Electron Devices; Dec. 2000; pp 2320-2325; vol. 47, No. 12; IEEE.

Affiliated with

Also associated with

Rating

Method of forming a transistor having multiple channels does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a transistor having multiple channels, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a transistor having multiple channels will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3421394