Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-04-12
2005-04-12
Lee, Hsien-Ming (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S637000, C438S643000, C438S644000
Reexamination Certificate
active
06878620
ABSTRACT:
Methods and apparatus for protecting the dielectric layer sidewalls of openings, such as vias and trenches, in semiconductor substrates are provided. A pre-liner and a liner are deposited over the sidewalls of the openings as part of integrated processing sequences that either do not remove the photoresist until subsequent processing or remove the photoresist with a plasma etch that does not contaminate the sidewalls of the openings.
REFERENCES:
patent: 4999096 (1991-03-01), Nihei et al.
patent: 5308793 (1994-05-01), Taguchi et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5486492 (1996-01-01), Yamamoto et al.
patent: 5933753 (1999-08-01), Simon et al.
patent: 5985762 (1999-11-01), Geffken et al.
patent: 6037664 (2000-03-01), Zhao et al.
patent: 6087705 (2000-07-01), Gardner et al.
patent: 6110648 (2000-08-01), Jang
patent: 6140226 (2000-10-01), Grill et al.
patent: 6165854 (2000-12-01), Wu
patent: 6188125 (2001-02-01), Havemann
patent: 6245661 (2001-06-01), Matsumoto et al.
patent: 6426289 (2002-07-01), Farrar
patent: 6448176 (2002-09-01), Grill et al.
patent: 6486059 (2002-11-01), Lee et al.
patent: 6509267 (2003-01-01), Woo et al.
patent: 6569760 (2003-05-01), Lin et al.
patent: 6583047 (2003-06-01), Daniels et al.
patent: 6693043 (2004-02-01), Li et al.
patent: 20010053602 (2001-12-01), Lee
patent: 20020060363 (2002-05-01), Xi et al.
patent: 20020064941 (2002-05-01), Chooi et al.
patent: 20020106895 (2002-08-01), Chung
patent: 20020164870 (2002-11-01), Cowley et al.
patent: 20030013297 (2003-01-01), Chen et al.
patent: 20030017695 (2003-01-01), Chen et al.
patent: 20030032278 (2003-02-01), Chen et al.
patent: WO 9852219 (1998-11-01), None
U.S. Appl. No. 08/856,116, filed May 14, 1997.
U.S. Appl. No. 10/196,498, filed Jul. 15, 2002.
“Voiding in Ultra Porous Low-k Materials Proposed Mechanism, Detection and Possible Solutions”, T. Jacobs, et al., from Proceedings of the IITC International Interconnect Technology Conference, Jun. 3-5, 2002 Hyatt Regency Airport Hotel, San Francisco, California pp. 236-238.
“Cross-Sectional Elastic Imaging and Defect Detection in Low-k Spin-on Dieletrics”, L. Muthuswami, et al., from Proceedings of the IITC International Interconnect Technology Conference, Jun. 3-5, 2002 Hyatt Regency Airport Hotel, San Francisco, California pp. 239-242.
“Porosity Effects on Low-k Dielectric Film Strength and Interfacial Adhesion”, G. Kloster, et al. from Proceedings of the IITC International Interconnect Technology Conference, Jun. 3-5, 2002 Hyatt Regency Airport Hotel, San Francisco, California pp. 242-244.
PCT International Search Report for PCT US/03/36048, dated Apr. 27, 2004 (AMAT/7668.PC).
Nemani Srinivas D.
Nguyen Son Van
Xia Li-Qun
Applied Materials Inc.
Lee Hsien-Ming
Moser Patterson & Sheridan
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