Method of making an integration of high voltage lateral MOS devi

Details Method of making an integration of high voltage lateral MOS devi Method of making an integration of high voltage lateral MOS devi

1995-06-07

1997-04-22

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438286, 438298, 438233, 438227, H01L 21265

Patent

active

056228783

ABSTRACT:
Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

REFERENCES:
patent: 4823173 (1989-04-01), Beasom
patent: 4918026 (1990-04-01), Kosiak et al.
patent: 5112765 (1992-05-01), Cederbaum et al.
patent: 5206535 (1993-04-01), Namose
patent: 5352620 (1994-10-01), Komori et al.

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