Method of forming a vertical power semiconductor device and...

Details Method of forming a vertical power semiconductor device and... Method of forming a vertical power semiconductor device and...

2005-01-11

2005-01-11

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S206000, C438S208000, C438S268000

Reexamination Certificate

active

06841437

ABSTRACT:
A method of forming medium breakdown voltage vertical transistors (11) and lateral transistors (12, 13) on the same substrate (14) provides for optimizing the epitaxial layer (16) for the lateral transistors (12, 13). The vertical transistor (11) is formed in a well (18) that has a lower resistivity than the epitaxial layer (16) to provide the required low on-resistance for the vertical power transistor (11).

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patent: 4881112 (1989-11-01), Matsushita
patent: 4896199 (1990-01-01), Tsuzuki et al.
patent: 5171699 (1992-12-01), Hutter et al.
patent: 5317180 (1994-05-01), Hutter et al.
patent: 6781804 (2004-08-01), Claverie

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