Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2005-09-20
2005-09-20
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S172000, C708S309000, C708S311000
Reexamination Certificate
active
06948043
ABSTRACT:
A method of optimizing performance of a memory subsystem in a computer system. This method including the step of informing the computer system of what type of memory module loading is present in the memory subsystem. The method also includes operating the memory subsystem at a first frequency that is at a chosen ratio to a second frequency at which a frontside bus (FSB) operates. Further, the method includes optimizing the performance of the memory subsystem by changing the ratio.
REFERENCES:
patent: 2001/0003198 (2001-06-01), Wu
patent: 2001/0014049 (2001-08-01), Woo et al.
Search Report issued on Dec. 18, 2003 in counterpart foreign application in GB under application No. 315099.2.
Barr Andrew H.
Espinoza-Ibarra Ricardo
Dinh Ngoc
Moazzami Nasser
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