Test method of semiconductor intergrated circuit and test...

Details Test method of semiconductor intergrated circuit and test... Test method of semiconductor intergrated circuit and test...

2005-07-26

2005-07-26

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06922803

ABSTRACT:
A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means110to generate identical pattern sequences repeatedly and means120to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns. Because a test pattern generator is provided independently of the circuit to be tested, the problem of a prolonged design period can be eliminated, a loss in the operating speed of the circuit under test is minimized and a high fault coverage can be achieved with less hardware overhead and a smaller volume of test data.

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Tsai et al., “STARBIST: Scan Autocorrelated Random Pattern Generation”, Department of Electrical & Computer Enginerring, University of CA, pp. 472-477.
Hellebrand et al., “Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers”, International test Conference 1992, paper 5.2, pp. 120-129.
Kiefer et al., “Deterministic BIST with Multiple Scan Chains”, Computer Auchitecture Lab, University of Stuttgart, pp. 1057-1064.a.

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