Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2005-09-20
2005-09-20
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
Reexamination Certificate
active
06946678
ABSTRACT:
A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.
REFERENCES:
patent: 5914512 (1999-06-01), Huang
patent: 6310361 (2001-10-01), Lichter
patent: 6339228 (2002-01-01), Iyer et al.
patent: 6812487 (2004-11-01), Wu et al.
patent: 6838296 (2005-01-01), Wu et al.
Huang Chien-Chang
Jiang Bo Ching
Ting Yu-Wei
Wu Tie Jiang
Nanya Technology Corporation
Quintero Law Office
Vu Hung
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