Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-04
2005-01-04
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S039000, C326S038000, C716S030000
Reexamination Certificate
active
06839873
ABSTRACT:
According to one embodiment, a programmable logic assembly (200) may include a nonvolatile memory (202) may be coupled to an associated volatile programmable logic device (PLD) (204). Built-in-self-test (BIST) data (208) may be stored in a nonvolatile memory (202) that places the volatile PLD (204) in a self-test configuration. If a volatile PLD (204) passes a self-test, user data (210) may be stored in a nonvolatile memory (202) that places a volatile PLD (204) into a user determined configuration.
REFERENCES:
patent: 4771399 (1988-09-01), Snowden et al.
patent: 5032533 (1991-07-01), Gill et al.
patent: 5652886 (1997-07-01), Tulpule et al.
patent: 5668816 (1997-09-01), Douskey et al.
patent: 5702988 (1997-12-01), Liang
patent: 5759877 (1998-06-01), Crafts et al.
patent: 5878051 (1999-03-01), Sharma et al.
patent: 5889701 (1999-03-01), Kang et al.
patent: 5909587 (1999-06-01), Tran
patent: 5946267 (1999-08-01), Pathak et al.
patent: 5970005 (1999-10-01), Yin et al.
patent: 5991907 (1999-11-01), Stroud et al.
patent: 6003150 (1999-12-01), Stroud et al.
patent: 6044025 (2000-03-01), Lawman
patent: 6046957 (2000-04-01), Shyu
patent: 6154864 (2000-11-01), Merritt
patent: 6202182 (2001-03-01), Abramovici et al.
patent: 6260139 (2001-07-01), Alfke
patent: 6401160 (2002-06-01), See et al.
patent: 6538468 (2003-03-01), Moore
patent: 6539510 (2003-03-01), St. Pierre et al.
patent: 6631487 (2003-10-01), Abramovici et al.
patent: 20020073372 (2002-06-01), Slezak et al.
Cook, A First Course in Digital Electronics, Prentice-Hall 1999, p. 684-689.*
Virtex 2.5 V: Field Programmable Gate Array, Datasheet DS003, Xilinx, 23 May 23, 2000, version 2.2.*
4 Mbit Virtual SPROM, Applicant Note XAPP079, Xilinx, Sep. 1997, version 2.2.*
Dynamic Reconfiguration, Application Note XAPP 093, Xilinx, Nov. 10, 1997, Version 1.1.
Cypress Semiconductor Corporation
Lamarre Guy J.
Sako Bradley T.
LandOfFree
Method and apparatus for programmable logic device (PLD)... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for programmable logic device (PLD)..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for programmable logic device (PLD)... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3394892