Method of manufacturing a vertical semiconductor device

Details Method of manufacturing a vertical semiconductor device Method of manufacturing a vertical semiconductor device

2005-09-27

2005-09-27

Loke, Steven (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S656000, C438S665000, C438S928000, C438S977000

Reexamination Certificate

active

06949434

ABSTRACT:
A method of manufacturing a vertical semiconductor device includes preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over the semiconductor substrate, forming a semiconductor element at a surface portion of the semiconductor layer, forming a first metal layer for a first electrode of the semiconductor element over the surface portion of the semiconductor layer, grinding a back of the semiconductor substrate to thin the semiconductor substrate and roughen a back surface of the semiconductor substrate, performing a wet etching upon the back surface; and forming on the back surface a second metal layer for a second electrode of the semiconductor element.

REFERENCES:
patent: 3858238 (1974-12-01), Nakamura et al.
patent: 3879230 (1975-04-01), Nakamura et al.
patent: 4751191 (1988-06-01), Gonsiorawski et al.
patent: 4853345 (1989-08-01), Himelick
patent: 4859629 (1989-08-01), Reardon et al.
patent: 4879250 (1989-11-01), Chan
patent: 4927784 (1990-05-01), Kazior et al.
patent: 4931412 (1990-06-01), Fischer et al.
patent: 4985740 (1991-01-01), Shenai et al.
patent: 5065216 (1991-11-01), Suzuki et al.
patent: 5077143 (1991-12-01), Barraclough et al.
patent: 5241862 (1993-09-01), Abbink et al.
patent: 5242862 (1993-09-01), Okabe et al.
patent: 5333961 (1994-08-01), Capigatti et al.
patent: 5338961 (1994-08-01), Lidow et al.
patent: 5663096 (1997-09-01), Okabe et al.
patent: 5689130 (1997-11-01), Okabe et al.
patent: 5994187 (1999-11-01), Okabe et al.
patent: 6114193 (2000-09-01), Chang et al.
patent: 6498366 (2002-12-01), Okabe et al.
patent: 57-15420 (1982-01-01), None
patent: 57-0907630 (1982-06-01), None
patent: 58-45814 (1983-10-01), None
patent: 59-189625 (1984-10-01), None
patent: 59-213140 (1984-12-01), None
patent: 59-220937 (1984-12-01), None
patent: 59-113629 (1985-06-01), None
patent: 61-230404 (1986-10-01), None
patent: 61-234041 (1986-10-01), None
patent: 61-296769 (1986-12-01), None
patent: 62-23170 (1987-01-01), None
patent: 62-43123 (1987-10-01), None
patent: 62-243332 (1987-10-01), None
patent: 62-293678 (1987-12-01), None
patent: 62-253633 (1988-10-01), None
patent: 1-169970 (1989-07-01), None
patent: 58-45814 (1993-10-01), None
patent: 59-220937 (1994-12-01), None
patent: 2-33367 (1995-10-01), None
patent: 63-253633 (1998-10-01), None
“Semiconductor devices-Physics and technology” by Sze, 1985, p. 302.
Krishina Shenai, “Vertical-Power DMOSFET”, IEEE Elect. Device Letter, vol. No. 10, No. 3,/1989.
Krishina Shenai, “Optimally Scaled Low-Voltage Vertical Power MOSFET's for High-Frequency Power Conversion”, IEEE Trans. of ELect. DEvice vol. 37, No. 4,4/1990.
C.Y. Ting et al., The Use of Titanium-based Contact Barrier Layers in Silicon Technology:, Thin Solid Films, 96(1982) 327-345 Electronics and Optics.
Semiconductor Devices-Physics and Technology , Jan. 1985 S.M. Sze p. 307.
Alvin B. Phillips, “Transistor Engineering and Introduction to Integrated Semiconductor Circuits,” p. 76.
S. Ogawa, et al. HRTEM and Non-Scale Micro Analysis of Titanium/Silicon Interfacial Reaction Correlated With Electrical Properties, Extended Abstract.
Wolf, et al. “Silicon Processing For The VLSI Era, vol. 1: Process Tech.”, Lattice Press, 1986.
K. Shenai, et al. “Characteristics of As Deposited and Sintered Mo/LPCVD W Contacts to as, B, and P Doped Silicon”, 1988 Materials Research Sociest, p. 219-224.
K. Shenai, et al., “Blanket LPCVD Tungsten Silicide Technology for Smart Power Applications”, IEEE Electron Device Letters, vol. 10, No. 6 1989, p. 270-273.
K. Shenai, et al. “High-Performance Vertical-Power DMOSFET's with Selectively Silicided Gate and Source Regions”, IEEE Electron Device Letters, vol. 10, No. 4 1989, p. 153-155.
K. Shenai, et al. “Selectively Silicided Vertical Power Double-Diffused Metal-Oxide Semiconductor Field Effect Transistors For High-Frequency Power Switching Applications”, j. Vac. Sci. Technol. B6(6), 1988, p. 1740-1745.
H.R. Change, et al., “Selectively Silicided Vertical Power UMOSFET's with a Specific On-REsistance of”, IEEE Transactions on Electron Devices, vol. ED-34, No. 11, 1987, p. 2329-2334.
K. Shenai, et al. “Selectively Silicided Vertical Power DMOSFET's for High-Frequency Power Conversion” Electronics Letters. vol. 25, No. 12, 1989, p. 784-785.
Webster's II New Riverside University Dictionary, 1984, p 549.
Semiconductor Devicea and Technology, by S.M. Sze, p. 38.
Office action dated Sep. 19, 2004 in co-pending U.S. Application No. 10/651,277.
“Semiconductor Devices —Physics and technology” by Sze, 1985, p. 302.

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