Timing of active pullup for dynamic semiconductor memory

Details Timing of active pullup for dynamic semiconductor memory Timing of active pullup for dynamic semiconductor memory

1980-02-06

1981-09-22

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

365204, G11C 700

Patent

active

042913926

ABSTRACT:
A method for operating a dynamic semiconductor memory circuit (10) having a memory cell (12) which comprises a access transistor (12a) connected to a half digit line (18) and a storage capacitor (12b). Each of the half digit lines (18, 22, 60 and 62) is charged or discharged as a result of either read operations carried out with the corresponding memory cells or write operations receiving incoming data states through input/output lines (42, 46). The charged state of the half digit line (18, 22, 60 and 62) is at a voltage substantially below that of the supply voltage of the circuit (10). After the half digit lines (18, 22, 60 and 62) are sensed and/or written to the desired states, a pullup circuit (48) for each of the half digit lines (18, 22, 60 and 62) charges the half digit lines with voltages above a predetermined threshold to the full supply voltage. A word line signal (72) couples the charge storage capacitor ( 12b) to the corresponding half digit line (18) to transfer the full supply voltage of the circuit (10) into the storage capacitor (12b).

REFERENCES:
patent: 3765002 (1973-10-01), Basse
patent: 3965460 (1976-06-01), Barbara
patent: 4070590 (1978-01-01), Ieda et al.
patent: 4168490 (1979-09-01), Stinehelfer

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