Semiconductor device for applying well bias and method of...

Details Semiconductor device for applying well bias and method of... Semiconductor device for applying well bias and method of...

2005-01-04

2005-01-04

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S758000, C257S763000

Reexamination Certificate

active

06838737

ABSTRACT:
A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the purity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.

REFERENCES:
patent: 6534864 (2003-03-01), Tanaka et al.
patent: 20020125577 (2002-09-01), Komada

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