Method of manufacturing semiconductor device having storage...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S238000, C438S253000, C438S250000, C438S244000, C438S791000, C438S787000

Reexamination Certificate

active

06844229

ABSTRACT:
A method of manufacturing a semiconductor device having a storage electrode of a capacitor is provided. The method includes the steps of: forming a contact hole perforating through an interlayer dielectric layer on a semiconductor substrate; forming a conductive plug to fill the contact hole and expose the surface of the interlayer dielectric layer; forming molds on the interlayer dielectric layer to expose the surface of the conductive plug; recessing the upper surface of the conductive plug to expose a portion of the sidewalls of the interlayer dielectric layer; forming an electrode layer to cover the recessed conductive plug, and the sidewalls of the interlayer dielectric layer and the molds; and removing upper surfaces of the electrode layer to make a storage electrode until molds are exposed. The method further includes the steps of: forming a conductive pad electrically connected to the semiconductor substrate and a lower insulating layer surrounding the conductive pad; and forming bit line stacks on the lower insulating layer, wherein the interlayer dielectric layer covers the bit line stacks, and the contact hole between the bit line stacks exposes the conductive pad.

REFERENCES:
patent: 6180452 (2001-01-01), Figura
patent: 6372575 (2002-04-01), Lee et al.
George A. Kaplita, Stefan Schmitz, Rajiv Ranade, and Swami Mathad, “Polysilicon Planarization and Plug Recess Etching in a Decoupled Plasma Source Chamber Using Two Endpoint Techniques,” MicroNews, vol. 6, No. 1, (2000) pp. 1-7.*
Gary E. McGuire, “Semiconductor Materials and Process Technology Handbook,” Noyes Publ., Norwich, New York (1988) pp. 210-265.*
IBM Technical Disclosure Bulletin, “Chemical Control of Reactive Ion Etch Selectivities,” vol. 32, No. 4A, (1989) pp. 354-355.*
IBM Technical Disclosure Bulletin, “Tapered Via Hole,” vol. 26, No. 12, (1983) p. 6282.*
IBM Technical Disclosure Bulletin, “Process for Polysilicon Emitter Transistor” vol. 26, 10A,(1984) pp. 5134-5135.*
Korean Patent Abstract—Publication No. 2001-0059014; Publication Date Jul. 6, 2001.

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