Method of forming a capacitor top plate structure to...

Details Method of forming a capacitor top plate structure to... Method of forming a capacitor top plate structure to...

2005-03-29

2005-03-29

Zarneke, David (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S381000

Reexamination Certificate

active

06872622

ABSTRACT:
A process for fabricating a capacitor under bit line (CUB), DRAM device, featuring increased capacitor storage node surface area, and increased overlay margin between storage node and bit line structures, has been developed. The process features the definition of hemispherical grain (HSG) silicon storage node shapes formed in storage node openings, and the definition of connecting HSG shapes formed in openings located adjacent to the storage node openings. This is accomplished dry etching procedures applied to portions of the HSG silicon layer not protected by a photoresist shape which in turn was obtained via partial exposure of, and development of, a photoresist layer. A polysilicon top plate structure, formed via polysilicon deposition and a following CMP procedure, results in a capacitor structure comprised with increased surface area as a result of the connected HSG silicon shapes. The ability to increase surface area via the connecting HSG silicon shapes allow ample space for definition of a bit line contact structure in a region located between capacitor structures.

REFERENCES:
patent: 5798289 (1998-08-01), Ajika et al.
patent: 5956587 (1999-09-01), Chen et al.
patent: 6159786 (2000-12-01), Chiang et al.
patent: 6200875 (2001-03-01), Jang et al.
patent: 6294426 (2001-09-01), Tu et al.

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