Circuit and method for testing high speed data circuits

Details Circuit and method for testing high speed data circuits Circuit and method for testing high speed data circuits

2005-05-17

2005-05-17

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C324S527000

Reexamination Certificate

active

06895535

ABSTRACT:
A circuit and method are described in which a DC voltage or current is connected to a high frequency, AC-coupled signal path between a transmitter and a receiver, and the bit error rate of the data transmission is tested while applying an altered bias voltage to the received signal. The bias voltage can be connected via a resistor, inductor or transistors. The transmitted signal is attenuated resistively, and a load capacitance is applied whose value causes digital transition times to exceed one unit interval. An intended application is testing of an integrated circuit, serializer/deserializer (serdes) operating above 1 GHz.

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Cai et al., “Jitter Testing for Gigabit Serial Communication Transceivers”, Design & Test, Jan.-Feb. 2003, p. 66-74, IEEE Circuits & Systems Society, USA.
Burns et al., “An Introduction to Mixed-Signal IC Test and Measurement”, Feb. 8, 2001, p. 399-400, Oxford University Press.

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