Increasing carrier mobility in NFET and PFET transistors on...

Details Increasing carrier mobility in NFET and PFET transistors on... Increasing carrier mobility in NFET and PFET transistors on...

2005-09-06

2005-09-06

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S783000, C438S788000, C438S791000

Reexamination Certificate

active

06939814

ABSTRACT:
Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

REFERENCES:
patent: 6573172 (2003-06-01), En et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2004/0075148 (2004-04-01), Kumagai et al.
patent: 2004/0104405 (2004-06-01), Huang et al.
patent: 2004/0113217 (2004-06-01), Chidambarrao et al.

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