Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-17
2005-05-17
Abraham, Fetsum (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S247000, C438S290000, C438S291000, C438S302000, C438S386000, C438S399000, C257S296000, C257S305000
Reexamination Certificate
active
06893921
ABSTRACT:
In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.
REFERENCES:
patent: 5402371 (1995-03-01), Ono
patent: 5856943 (1999-01-01), Jeng
patent: 5901084 (1999-05-01), Ohnakado
patent: 6057575 (2000-05-01), Jenq
patent: 6130129 (2000-10-01), Chen
patent: 6134144 (2000-10-01), Lin et al.
patent: 6171909 (2001-01-01), Ding et al.
patent: 6200856 (2001-03-01), Chen
patent: 6236082 (2001-05-01), Kalnitsky et al.
patent: 6261903 (2001-07-01), Chang et al.
patent: 6266278 (2001-07-01), Harari et al.
patent: 6326661 (2001-12-01), Dormans et al.
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6365457 (2002-04-01), Choi
patent: 6414872 (2002-07-01), Bergemont et al.
patent: 6420231 (2002-07-01), Harari et al.
patent: 6437360 (2002-08-01), Cho et al.
patent: 6438036 (2002-08-01), Seki et al.
patent: 6444525 (2002-09-01), Lee
patent: 6486023 (2002-11-01), Nagata
patent: 6518618 (2003-02-01), Fazio et al.
patent: 6541324 (2003-04-01), Wang
patent: 6541829 (2003-04-01), Nishinohara et al.
patent: 20020064071 (2002-05-01), Takahashi et al.
patent: 20020197888 (2002-12-01), Huang et al.
patent: 20030218908 (2003-11-01), Park et al.
patent: 20040004863 (2004-01-01), Wang
patent: 0 938 098 (1999-08-01), None
Ma, Yale et al., “A Dual-Bit Split-Gate EEPROM (DS'G) Cell in Contactless Array for Single Vcc High Density Flash Memories,” 1994 IEEE, 3.5.1-3.5.4.
Spinelli, Alessandro S., “Quantum-Mechanical 2D Simulation of Surface-and Buried-Channel p-MOS,”2000 International Conference on Simulation of Semiconductor Processes and Devices: SISPAD 2000. Seattle, WA Sep. 6-8, 2000.
Kim, K.S. et al. “A Novel Dual String NOR (DuSnor) Memory Cell Technolgy Scalable to the 256 Mbit and 1 Gbit Flash Memories,” 1995 IEEE 11.1.1-11.1.4.
Bergemont, A. et al.“NOR Virtual Ground (NVG)- A New Scaling Concept for Very High Density FLAS EEPROM and its Implementation in a 0.5 um Process,” 1993 IEEE 2.2.1-2.2.4.
Van Duuren, Michiel et al., “Compact poly-CMP Embedded Flash Memory Cells For One or Two Bit Storage,” Philips Research Leuven, Kapeldreef 75, B3001 Leuven, Belgium, pp. 73-74.
U.S. Appl. No. 10/440,466, entitled “Fabrication Of Conductive Gates For Nonvolatile Memories From Layers With Protruding Portions,” filed May 16, 2003.
U.S. Appl. No. 10/440,005, entitled “Fabrication of Dielectric On A Gate Surface To Insulate The Gate From Another Element Of An Integrated Circuit,” filed May 16, 2003.
U.S. Appl. No. 10/440,508, entitled “Fabrication Of Gate Dielectric In Nonvolatile Memories Having Select, Floating And Control Gates,” filed May 16, 2003.
U.S. Appl. No. 10/440,500, entitled “Integrated Circuits With Openings that Allow Electrical Contact To Conductive Features Having Self-Aligned Edges,” filed May 16, 2003.
U.S. Appl. No. 10/393,212, entitled “Nonvolatile Memories And Methods Of Fabrication,” filed Mar. 19, 2003.
U.S. Appl. No. 10/393,202, entitled “Fabrication of Integrated Circuit Elements In Structures With Protruding Features,” filed Mar. 19, 2003.
U.S. Appl. No. 10/631,941, entitled “Nonvolatile Memory Cell With Multiple Floating Gates Formed After The Select Gate,” filed Jul. 30, 2003.
U.S. Appl. No. 10/632,155, entitled “Nonvolatile Memory Cells With Buried Channel Transistors,” filed Jul. 30, 2003.
U.S. Appl. No. 10/632,007, entitled “Arrays Of Nonvolatile Memory Cells Wherin Each Cell Has Two Conductive Floating Gates,” filed Jul. 30, 2003.
U.S. Appl. No. 10/631,452, entitled “Fabrication Of Dielectric For A Nonvolatile Memory Cell Having Multiple Floating Gates,” filed Jul. 30, 2003.
U.S. Appl. No. 10/632,154, entitled “Fabrication Of Gate Dielectric In Nonvolatile Memories In Which A Memory Cell Has Multiple Floating Gates,” filed Jul. 30, 2003.
U.S. Appl. No. 10/631,552, entitled “Nonvolatile Memories And Methods Of Fabrication,” filed Jul. 30, 2003.
U.S. Appl. No. 10/632,186, entitled “Nonvolatile Memory Cell With Multiple Floating Gates Formed After The Select Gate And Having Upward Protrusions,” filed Jul. 30, 2003.
U.S. Appl. No. 10/393,212, filed Mar. 19, 2003 entitled “Nonvolatile Memories And Methods of Fabrication.”
U.S. Appl. No. 10/393,202, filed Mar. 19, 2003, entitled “Fabrication of Integrated Circuit Elements In Structures With Protruding Features.”
Naruke, K.; Yamada, S.; Obi, E.; Taguchi, S.; and Wada, M. “A New Flash-Erase EEPROM Cell with A Sidewall Select-Gate On Its Source Side,” 1989 IEEE, pp. 604-606.
Wu, A.T.; Chan T.Y.; Ko, P.K.; and Hu, C. “A Novel High-Speed. 5-Volt Programming EPROM Structure With Source-Side Injection,” 1986 IEEE, 584-587.
Mizutani, Yoshihisa: and Makita, Koji “A New EPROM Cell With A Sidewall Floating Gate Fro High-Density and High Performance Device,” 1985 IEEE, 635-638.
Ma, Y.; Pang, C.S.: Pathak, J.: Tsao, S.C.: Chang, C.F.; Yamauchi, Y.; Yohsimi, M. “A Novel High Density Contactless Flash Memory Array Using Split-Gate Source-Side-Injection Cell for 5V-Only Applications,” 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 49-50.
Shirota, Riichiro “A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend,” Feb. 2000, Nonvolatile Memory Workshop in Monterey, California.. pp. 22-31.
Mih, Rebecca et al, “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 120-121.
U.S. Appl. No. 10/798,475, entitled “Fabrication of Conductive Lines Interconnecting Conductive Gates in Nonvolatile Memories and Non-Volatile Memory Structures,” filed Mar. 10, 2004.
U.S. Appl. No. 10/797,972, entitled “Fabrication of Conductive Lines Interconnecting First Conductive Gates in Nonvolatile Memories Having Second Conductive Gates Provided By Conductive Gates Lines, Wherein The Adjacent Conductive Gate Lines For The Adjacent Columns Are Spaced From Each Other, And Non-Volatile Memory Structures,” filed Mar. 10, 2004.
Abraham Fetsum
MacPherson Kwok & Chen & Heid LLP
Mosel Vitelic Inc.
Shenker Michael
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