Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-07-05
2005-07-05
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000
Reexamination Certificate
active
06913977
ABSTRACT:
A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa, leaving a portion of the drain abutting the trench. The body region in the second mesa includes a channel region adjacent a wall of the trench. The area where the drain abuts the trench is thus relatively restricted and the drain-gate capacitance of the device is reduced. Moreover, the drain-gate capacitance is made independent of the depth and width of the trenches, allowing greater freedom in the design of the MOSFET.
REFERENCES:
patent: 4084175 (1978-04-01), Ouyang
patent: 4272302 (1981-06-01), Jhabvala
patent: 6521498 (2003-02-01), Zandt In't et al.
patent: 6690062 (2004-02-01), Henninger et al.
Hoang Quoc
Silicon Valley Patent & Group LLP
Siliconix incorporated
LandOfFree
Triple-diffused trench MOSFET and method of fabricating the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Triple-diffused trench MOSFET and method of fabricating the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Triple-diffused trench MOSFET and method of fabricating the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3372816