Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2003-06-30
2004-11-16
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S207000
Reexamination Certificate
active
06819600
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Patent Application No. 2002-37851, filed on Jul. 2, 2002, the contents of which are herein incorporated by reference in their entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This disclosure relates to integrated circuit devices, and in particular to a semiconductor memory device that is capable of stable operation at a low power supply voltage.
2. Description of the Related Art
One of the essential circuits for realizing high-performance DRAMs is a bit line sense amplifier circuit. In a DRAM read operation, as understood by those skilled in the art, a small amount of charge is transferred from a memory cell to a bit line, and a sense amplifier senses and amplifies the voltage on the bit line. In the case of high-density DRAMs, it is increasingly difficult to perform a stable read operation because signal charges stored in a memory cell are reduced, owing to decreases in cell size and operating voltage. Therefore, a sense amplifier with higher sensitivity than presently available is necessary.
Because of its simple structure and high sensitivity, a dynamic cross-coupled sense amplifier (hereinafter referred to as a flip-flop sense amplifier) has been widely used as a bit line sense amplifier. The sensitivity of a sense amplifier is affected by imbalanced device parameters, for example, the threshold voltage and transconductance inconsistency between paired transistors. In the case of high-density DRAMs, this imbalance is increased because a large number of transistors with a scaled-down feature size are used in the high-density DRAM. An offset voltage of a flip-flop sense amplifier results from the device parameter imbalance. The offset voltage of the flip-flop sense amplifier causes a reduced sensing margin.
In general, in cases where an offset voltage of a sense amplifier is lower than a bit line voltage induced by charge sharing between capacitance of a memory cell and capacitance of a bit line, read/refresh operations are performed normally. On the other hand, in cases where the offset voltage of the sense amplifier is higher than the induced bit line voltage, the read/refresh operations are not carried out normally. This means that an offset voltage of a sense amplifier gives rise to a decrease in the sensing margin. The decrease in the sensing margin limits the store or refresh time. In cases where a memory device operates at a low power supply voltage, the sensitivity of the sense amplifier is greatly affected by the offset voltage because the voltage induced on a bit line is relatively reduced.
Various circuit techniques have been proposed that minimize the impact upon the imbalance or offset voltage owing to a flip-flop sense amplifier. One such circuit technique is to compensate for the threshold voltage mismatch of paired sense transistors by adjusting a bit line precharge level. This technique obtains high sensitivity only in cases where the imbalance is caused by an imbalance between threshold voltages. Another technique is to suppress the overall electric imbalance of a sense amplifier by adopting a simple offset compensation, which is disclosed in the IEEE Journal of Solid-State Circuits, Vol. 29 No. 1, pp. 9-13 January 1994, entitled “OFFSET COMPENSATING BIT-LINE SENSING SCHEME FOR HIGH DENSITY DRAM'S”.
An offset compensating bit-line sensing (OCS) scheme disclosed in the reference can remove the overall electric imbalance of paired transistors of a sense amplifier. In the OCS scheme, a differential amplifier for compensating an offset voltage of a sense amplifier is disposed in a sense amplification region. In case of high-density DRAM's, however, it is difficult to include a sense amplifier of the OCS scheme in a limited sense amplification region using present process techniques.
Embodiments of the invention overcome this and other limitations in the prior art.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a layout structure for an offset-compensated amplifier circuit that enables a flip-flop sense amplifier to perform a stable sensing operation irrespective of its own offset voltage.
Other embodiments of the invention provide a semiconductor memory device that includes an offset-compensated amplifier circuit. The offset-compensated amplifier circuit enables a flip-flop sense amplifier to perform a stable sensing operation irrespective of its own offset voltage. A part of the offset-compensated amplifier circuit is situated at, for example, a same region where the flip-flop sense amplifier is, and the other part situated at, for example, a region where drivers related to the flip-flop sense amplifier are. For example, the drivers include PEQ drivers, LA and LAB drivers, and so on. With this distributed arrangement, offset-compensated amplifier circuits can be obtained.
REFERENCES:
patent: 5177453 (1993-01-01), Russell et al.
Article from IEEE Journal of Solid-State Circuits, vol. 29 No. 1, pp. 9-13 Jan. 1994, entitled “Offset Compensating Bit-Line Sensing Scheme For High Density Dram's”.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Tran M.
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