Semiconductor device and nonvolatile semiconductor memory...

Details Semiconductor device and nonvolatile semiconductor memory... Semiconductor device and nonvolatile semiconductor memory...

2001-08-03

2004-08-31

Jackson, Jerome (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S261000, C438S264000, C438S287000, C438S591000, C438S593000

Reexamination Certificate

active

06784057

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a nonvolatile semiconductor memory device and process for the same, in particular, to a semiconductor device and a nonvolatile semiconductor memory device where it is possible to simplify the manufacturing processes thereof as well as those processes.
2. Description of the Background Art
Conventionally, a nonvolatile semiconductor memory device is known as one type of semiconductor devices.
FIG. 15
is a schematic cross section view showing a conventional nonvolatile semiconductor memory device. Referring to
FIG. 15
, the conventional nonvolatile semiconductor memory device is described.
Referring to
FIG. 15
, the nonvolatile semiconductor memory device includes a memory cell region and a peripheral circuit region. In the memory cell region, shown in
FIG. 15
, a cross section view A showing a region where a plurality of memory cells are formed and a cross section view B which is a cross section view along the line B—B in the above cross section view A are shown. Cross section view A is a cross section view in the bit line direction (direction approximately parallel to the direction in which interconnections
125
a
to
125
c
extend) in the memory cell region. Cross section view B is a cross section view in the word line direction (direction approximately perpendicular to the direction in which a phosphorous doped polysilicon film
116
a
to
116
d
extends as control gate electrodes) in the memory cell region.
In the memory cell region, an n well
105
is formed in a region at a predetermined depth from the main surface of a semiconductor substrate
101
. A p well
111
a
is formed in a region located above the n well
105
in the semiconductor substrate
101
. An element isolation insulating film
102
a,
102
b
are formed on the main surface of the semiconductor substrate
101
. As is seen from cross section views A and B, n type diffusion regions
120
a
to
120
c
are formed in the main surface of the semiconductor substrate
101
at predetermined intervals in the direction perpendicular to the surface of the paper in cross section view A. A silicon oxide film
112
is formed on the main surface of the semiconductor substrate
101
. A polysilicon film
113
ab,
113
bb,
113
cb
which become floating gate electrodes is formed on the silicon oxide film
112
. This polysilicon film
113
ab,
113
bb,
113
cb
as floating gate electrodes is formed of a plurality of pieces arranged at intervals in the direction perpendicular to the surface of the paper in cross section view A. That is to say, as shown in cross section view B, the pieces of polysilicon film
113
ba,
113
bb,
113
bc,
113
bd
are arranged at intervals with interstitial regions wherein the n type diffusion regions
120
a
to
120
c
are formed. A three layered insulating film
115
a
to
115
d
is formed as an intermediate insulating film on the polysilicon film
113
ab,
113
bb,
113
cb,
113
ba,
113
bc,
113
bd
as the floating gate electrodes. This three layered insulating film
115
a
to
115
d
is formed of a three layered structure of a silicon oxide film, a silicon nitride film and a silicon oxide film. A phosphorous doped polysilicon film
116
a
to
116
d
as control gate electrodes are formed on the above three layered insulating film
115
a
to
115
d.
A tungsten silicide (WSi) film
117
a
to
117
d
is formed on the phosphorous doped polysilicon film
116
a
to
116
d.
A silicon oxide film
118
a
to
118
d
are formed on the tungsten silicide film
117
a
to
117
d.
A boron phosphorous glass
123
is formed on the silicon oxide film
118
a
to
118
d.
Contact holes
124
a
to
124
c
are formed by partially removing portions of the boron phosphorous glass
123
and the silicon oxide film
112
in the regions located above the n type diffusion regions
120
a
to
120
c.
At the bottom of these contact holes
124
a
to
124
c,
the surfaces of the n type diffusion regions
120
a
to
120
c
are exposed. Interconnections
125
a
to
125
c
made of a conductive material are formed so as to extend from the inside of these contact holes
124
a
to
124
c
to the upper surface of the boron phosphorous glass
123
. As for the material for these interconnections
125
a
to
125
c,
an aluminum-silicon-copper (Al—Si—Cu) alloy film can be used.
In cross section view B, of the memory cell region, the n type diffusion region
120
a
and the n type diffusion region (not shown) located on the left side of the above n type diffusion region
120
a
work as the source region and the drain region of one flash memory cell. These n type diffusion regions, the silicon oxide film
112
, which works as a tunnel insulating film, the phosphorous doped polysilicon film
113
ba
as a floating gate electrode, the three layered insulating film
115
a
and the phosphorous doped polysilicon film
116
a
as a control gate electrode form one flash memory cell. In addition, the n type diffusion regions
120
a,
120
b
as the source and drain regions, the silicon oxide film
112
which works as a tunnel insulating film, the phosphorous doped polysilicon film
113
bb
as a floating gate electrode, the three layered insulating film
115
b
and the phosphorous doped polysilicon film
116
b
as a control gate electrode form another flash memory cell. In addition, the n type diffusion regions
120
b,
120
c
as the source and drain regions, the silicon oxide film
112
which works as a tunnel insulating film, the phosphorous doped polysilicon film
113
bc
as a floating gate electrode, the three layered insulating film
115
c
and the phosphorous doped polysilicon film
116
c
as a control gate electrode form another flash memory cell. Furthermore, the n type diffusion region
120
c
and an n type diffusion region (not shown) arranged on the right side of the n type diffusion region
120
c
with an interval between them as the source and drain regions, the silicon oxide film
112
which works as a tunnel insulating film, the phosphorous doped polysilicon film
113
bd
as a floating gate electrode, the three layered insulating film
115
d
and the phosphorous doped polysilicon film
116
d
as a control gate electrode form still another flash memory cell. The flash memory cells are arranged in a matrix form in the memory cell region.
In the peripheral circuit region of the nonvolatile semiconductor memory device shown in
FIG. 15
, an n type field effect transistor (FET)
126
and a p type FET
127
are formed. In the peripheral circuit region, an element isolation insulating film
102
c
is formed on the main surface of the semiconductor substrate
101
. In the element formation region isolated by this element isolation insulating film
102
c,
a p well
111
b
is formed in the main surface of the semiconductor substrate
101
in the region where the n type FET
126
is formed. Then type diffusion regions
121
a
and
121
b
which become the source and drain regions of the n type FET
126
are formed with a channel region between them in the main surface of the semiconductor substrate
101
in this p well
111
b.
A silicon oxide film
129
is formed as a gate insulating film on the main surface of the semiconductor substrate
101
. A phosphorous doped polysilicon film
116
e
is formed on the silicon oxide film
129
as a gate electrode in the region above the channel region located between the n type diffusion regions
121
a
and
121
b
which become the source and drain regions. A tungsten silicide film
117
e
is formed on the phosphorous doped polysilicon film
116
e.
A silicon oxide film
118
e
is formed on the tungsten silicide film
117
e.
In the region wherein the p type FET
127
is formed in the peripheral circuit region, an n well
108
is formed in the semiconductor substrate
101
. P type diffusion regions
122
a
and
122
b,
which become the source and drain regions, are formed so as to face each other via a channel region in the main surface of the semiconductor substrate
101
in the above n well
108

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