Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-05-03
2004-08-10
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000
Reexamination Certificate
active
06773990
ABSTRACT:
1. TECHNICAL FIELD
The present invention is generally in the field of semiconductor fabrication. More specifically, the present invention is in the field of fabrication of semiconductor memory cells.
2. BACKGROUND ART
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash memory devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash memory devices enable the simultaneous erasing of all memory cells.
Product development efforts in flash memory devices have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, and reducing cell dimensions. By reducing cell dimensions, flash memory devices can achieve increased speed and reduced power consumption. As the flash memory cell is reduced in size, the flash memory cell's channel length is also reduced in size. By way of background, in a floating gate flash memory cell, the channel length refers to the length of the region situated between source and drain junctions of the flash memory cell that is controlled by the flash memory cell's floating gate. As the channel length of the memory cell decreases, the source and drain regions of the memory cell become effectively closer to each other, which can cause undesirable short channel effects. For example, the short channel effect known as “punch through” occurs when a high drain voltage causes uncontrolled current, i.e. current that is not controlled by the memory cell's floating gate, to flow. Punch through can start to occur at channel lengths less than 0.5 micron, for example. Drain induced barrier lowering (“DIBL”) is another undesirable short channel effect that starts to occur as channel length decreases. As a result of DIBL, the memory cell's effective threshold voltage decreases, which undesirably affects the performance of the memory cell.
In CMOS devices, two conventional techniques utilized to reduce short channel affects, such as punch through and DIBL, are halo doping and retrograde well doping. In halo doping, a high concentration of P type dopant is implanted, for example, close to source and drain junctions of an N-channel device, such as an NFET. The high concentration of P type dopant implanted around the source and drain junctions reduces short channel effects, such as punch through and DIBL, by making the depletion region between source and drain junctions much smaller. In retrograde well doping, a high concentration of P type dopant is formed below the substrate surface at a depth in a P well where punch through can occur in an N-channel device, such as an NFET. As a result, the high concentration of P type dopant in the P well reduces the effective width of the depiction region between source and drain junctions, which reduces punch through in the N-channel device. However, the high concentration of P type dopant situated close of the drain junction in the conventional halo doping and retrograde well doping techniques can cause undesirable drain junction breakdown.
Also, the conventional halo and retrograde well doping techniques discussed above are difficult to apply to floating gate flash memory cells having small dimensions, since the implanted P type dopant diffuses quickly.
Thus, there is a need in the art for an effective method for reducing short channel effects in memory cells, such as floating gate flash memory cells.
SUMMARY
The present invention is directed to method for reducing short channel effects in memory cells and related structure. The present invention addresses and resolves the need in the art for an effective method for reducing short channel effects in memory cells, such as floating gate flash memory cells.
According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The floating gate memory array may be a floating gate flash memory array, for example. The dielectric material may be removed, for example, in a self-aligned source etch. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region.
The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region. The P type dopant can be boron, for example. The P type dopant can be implanted at an angle of between approximately 45.0 degrees and approximately 90.0 degrees with respect to a top surface of the first source region, for example. The P type dopant is not implanted in a drain region, where the drain region is separated from the first source region by a word line. The method further comprises performing a thermal cycle, where the thermal cycle causes the P type dopant to form a retrograde profile underneath the N+ type region and a graded concentration profile adjacent to the N+ type region.
In one embodiment, the invention is a floating gate memory array fabricated by utilizing the above discussed method. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
REFERENCES:
patent: 6410389 (2002-06-01), Cappelletti et al.
Fastow Richard
He Yue-Song
Mizutani Kazuhiro
Thurgate Timothy
Advanced Micro Devices , Inc.
Farjami & Farjami LLP
Le Dung A.
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