Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-08-26
2004-11-16
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S370000, C438S526000
Reexamination Certificate
active
06818490
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices. More specifically, the present invention relates to high voltage field-effect transistor structures fabricated in silicon substrates.
BACKGROUND OF THE INVENTION
Lateral, high-voltage, field-effect transistors (HVFETs) have been fabricated using an insulated gate field-effect transistor (IGFET) placed in series with a high-voltage junction field-effect transistor (JFET). The IGFET is used to control the “on” state current in the device and the JFET is used to support high-voltage in the “off” state. This HVFET structure can be switched at high voltages, has a low on-state resistance, and has insulated-gate control. In addition, it may advantageously be fabricated near low voltage logic transistors on a single integrated circuit chip.
Lateral HVFETs are commonly fabricated in accordance with the Reduced Surface Field (RESURF) principle. The RESURF principle, however, mandates that the charge in the extended drain region, which serves as the channel of a lateral JFET, be carefully controlled to obtain high breakdown voltage. To keep the maximum electric field below the critical field at which avalanche breakdown occurs the amount of charge in the JFET channel is typically limited to a maximum of about 1×10
12
cm
−2
. When the HVFET is in the “on” state, the resistance of the JFET channel constitutes a large portion of the on-state resistance of the HVFET. Therefore, the limitation on the maximum charge in the JFET channel also sets the minimum specific on-resistance of the device.
A HVFET having an extended drain region with a top layer of a conductivity type opposite that of the extended drain region is disclosed in U.S. Pat. No. 4,811,075. The '075 patent teaches that the top layer nearly doubles the charge in the conducting layer, with a commensurate reduction in device on-resistance. This top layer also helps to deplete the JFET conduction region when the extended drain is supporting a high voltage.
Further extending this concept, U.S. Pat. No. 5,411,901 teaches utilizing the opposite conductivity type top layer as the conducting portion of the JFET in a complementary high-voltage transistor. One drawback, however, is that construction of this complementary device requires additional processing steps to achieve high-voltage capability. Additionally, the on-resistance of the complementary device is limited by the charge requirement for the top region (e.g., about 1×10
12
cm
−2
). Another difficulty is that the top layer is often formed prior to oxidation of the silicon surface, which introduces additional process variation.
To further increase the total charge in the conducting region of the JFET and reduce on-resistance, U.S. Pat. No. 5,313,082 teaches a HVFET structure in which two JFET channels are arranged in parallel. A triple diffusion process is disclosed, in which three separate implant and diffusion steps are required to form a HVFET having an N-type conducting top layer, a P-type middle layer, and an N-type conducting bottom layer. The multiple layers of alternating conductivity types are fabricated by implanting, and then diffusing, dopants into the semiconductor substrate. The '082 patent also describes a complementary high-voltage transistor (i.e., a P-channel device) that is formed by adding an additional layer to the three-layer extended drift region.
One shortcoming of this prior art approach is that each successive layer is required to have a surface concentration that is higher than the preceding layer, in order to fully compensate and change the conductivity type of the corresponding region. Diffusion of dopants from the surface makes it very difficult to maintain adequate charge balance among the layers. In addition, the heavily doped P-N junction between the buried layer and drain diffusion region degrades the breakdown voltage of the device. The concentrations also tend to degrade the mobility of free carriers in each layer, thereby compromising the on-resistance of the HVFET. The additional layer required for making the complementary device also complicates the manufacturing process.
A p-channel MOS device design that is compatible with a generic process for manufacturing complementary CMOS devices is disclosed in U.S. Pat. No. 5,894,154.
REFERENCES:
patent: 4618541 (1986-10-01), Forouhi et al.
patent: 4626879 (1986-12-01), Colak
patent: 4665426 (1987-05-01), Allen et al.
patent: 4754310 (1988-06-01), Coe
patent: 4764800 (1988-08-01), Sander
patent: 4811075 (1989-03-01), Eklund
patent: 4890146 (1989-12-01), Williams et al.
patent: 4922327 (1990-05-01), Mena et al.
patent: 4926074 (1990-05-01), Singer et al.
patent: 4939566 (1990-07-01), Singer et al.
patent: 4963951 (1990-10-01), Adler et al.
patent: 4967246 (1990-10-01), Tanaka
patent: 5010024 (1991-04-01), Allen et al.
patent: 5025296 (1991-06-01), Fullerton et al.
patent: 5040045 (1991-08-01), McArthur et al.
patent: 5068700 (1991-11-01), Yamaguchi et al.
patent: 5146298 (1992-09-01), Eklund
patent: 5155574 (1992-10-01), Yamaguchi
patent: 5237193 (1993-08-01), Williams et al.
patent: 5258636 (1993-11-01), Rumennik et al.
patent: 5270264 (1993-12-01), Andideh et al.
patent: 5313082 (1994-05-01), Eklund
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5349225 (1994-09-01), Redwine et al.
patent: 5359221 (1994-10-01), Miyamoto et al.
patent: 5386136 (1995-01-01), Williams et al.
patent: 5411901 (1995-05-01), Grabowski et al.
patent: 5521105 (1996-05-01), Hsu et al.
patent: 5550405 (1996-08-01), Cheung et al.
patent: 5637898 (1997-06-01), Baliga
patent: 5654206 (1997-08-01), Merrill
patent: 5656543 (1997-08-01), Chung
patent: 5659201 (1997-08-01), Wollesen
patent: 5663599 (1997-09-01), Lur
patent: 5670828 (1997-09-01), Cheung et al.
patent: 5679608 (1997-10-01), Cheung et al.
patent: 5716887 (1998-02-01), Kim
patent: 5894154 (1999-04-01), Shibib
patent: 5943595 (1999-08-01), Akiyama et al.
patent: 5998833 (1999-12-01), Baliga
patent: 6010926 (2000-01-01), Rho et al.
patent: 6168983 (2001-01-01), Rumennik et al.
patent: 6184555 (2001-02-01), Tihanyi et al.
patent: 6207994 (2001-03-01), Rumennik et al.
patent: 6465291 (2002-10-01), Disney
patent: 43 09 764 (1994-09-01), None
patent: 56-38867 (1981-04-01), None
patent: 57-10975 (1982-01-01), None
patent: 57-12557 (1982-01-01), None
patent: 57-12558 (1982-01-01), None
patent: 60-64471 (1985-04-01), None
patent: 3-211771 (1991-09-01), None
patent: 4-1078677 (1992-04-01), None
patent: 6-224426 (1994-08-01), None
patent: WO 99/34449 (1999-07-01), None
“International Electron Devices Meeting 1979- Washington, D.C, Dec. 3-4-5, ” Sponsored by Electron Devices Society of IEEE, pp. 238-241.
“Realization of High Breakdown of Voltage (>700V) in Thin SOI Devices, ” S. Merchant, et al., Phillips Laboratories North America, 1991 IEEE, pp. 31-35.
“Theory of Semiconductor Superjunction Devices, ” T. Fujuhana, Japanese Journal of Applied Physics, Part 1, Oct. 1997, vol. 36, No. 10, pp. 6254-6262.
“Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance, ” B. Shieh, et al., IEEE Electron Device Letters, vol. 19, No. 1, Jan. 1998.
“Oxide-Bypassed VDMOS (OBVDMOS) : An Alternative to Superjunction High-Voltage MOS Power Devices, ” Yung C. Liang, et al., IEEE Electron Devices Letters, vol. 22, No. 8, Aug. 8, 2001, pp. 407-409.
“Comparison of High-Voltage Devices for Power Integrated Circuits, ” R. Jayaraman, et al., IEDM 84, 1984, pp. 258-261.
“A New Generation of High-Voltage MOSFETs Breaks the Limit Line of Silicon, ” G. Debby, et al., Siemens AG, Munchen, Germany, IEDM 98-683 -IEDM 98-685.
“High Performance 600 V Smart Technology Based onThin Layer Silicon-on-Insulator,” T. Letavic, et al., Phillips Electronics North America Corp., 4 Pages.
“Modern Semiconductor Device Physics,” S. M. Sze, John Wiley & Sons, 1998, Chapter 4, pp. 203-206.
“Modeling Optimization of Lateral High Voltage IC Devices to Minimize 3-D Effects,” H. Yilmaz, R&D Engineering, GE Corp., NC, pp. 290-297.
Burgess & Bereznak LLP
Loke Steven
Power Integrations, Inc.
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