Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-27
2004-08-03
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000
Reexamination Certificate
active
06770533
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a method of manufacturing a semiconductor device, a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein a buried diffusion layer serves as a signal line.
2. Description of the Related Art
Semiconductor memory devices known as typical semiconductor devices are classified into two types: volatile memories; and, nonvolatile memories. Of these memories, whereas the volatile ones lose their stored data when their power source is turned off, the nonvolatile ones may keep their stored data even when their power source is turned off. The former or volatile memories are known as RAMs (i.e., Random Access Memories), and the latter or nonvolatile memories are known as ROMs (i.e., Read Only Memories).
Of the above-mentioned semiconductor devices, particularly the ROMs are used in various types of information processing apparatuses. Of these ROMs, EPROMs (i.e., Erasable and Programmable ROMs)” and EEP (i.e., Electrically Erasable and Programmable ROMs) are widely known. In the EPROMs, their stored information may be erased by applying ultraviolet rays thereto, and also may be electrically stored therein again. On the other hand, in the EEPs, their stored information may be electrically erased and stored therein again. Further, of the EEPROMS, ones capable of performing information's block erasing and byte writing operations are known as flash memories, which are noted for their abilities to replace the floppy disks and the hard disks both typical of conventional memory means.
Any one of such writable and nonvolatile semiconductor memory devices has an MIS (i.e., Metal Insulator Semiconductor) type construction, in which a metallic gate has a laminated construction and is therefore constructed of: a floating gate buried in an insulation film; and, a control gate formed over this floating gate through the insulation film. In operation, information is stored in a memory cell of the nonvolatile semiconductor memory device by injecting an electric charge into the floating gate of the memory cell which is electrically isolated from the other memory cells in the semiconductor memory device, wherein the floating gate may keep the electric charge thus injected therein even when its power source is turned off.
In such a conventional type of nonvolatile semiconductor memory device and a method of manufacturing the same as those disclosed in Japanese Patent Laid-Open No. Hei 6-283721, for example: buried diffusion layers are formed in a semiconductor region so as to be disposed adjacent to opposite end portions of the floating gate described above, so that the buried diffusion layers are used as bit lines of the semiconductor memory device.
FIG. 30
shows a plan view of the above-mentioned conventional type of nonvolatile semiconductor memory device.
FIG. 31
shows a cross-sectional view of the conventional nonvolatile semiconductor memory device, taken along the line A—A of FIG.
30
. As shown in
FIGS. 30 and 31
, for example, in an active region defined by a device isolation region or oxide film
52
formed in a P-type semiconductor substrate
51
, a first floating gate
54
and a second floating gate
55
are formed side by side and insulated from each other through a gate oxide film
53
. Formed in the P-type semiconductor substrate
51
so as to be disposed adjacent to outer end portions of both the first floating gate
54
and the second floating gate
55
are N-type drain regions
56
,
57
. Further, formed in the P-type semiconductor substrate
51
so as to be disposed between the first floating gate
54
and the second floating gate
55
is an N-type source region
58
. A first memory transistor is constructed of the first floating gate
54
, N-type drain region
56
and the N-type source region
58
. On the other hand, a second memory transistor is constructed of the second floating gate
55
, N-type drain region
57
and the N-type source region
58
. As is clear from the above, the N-type source region
58
is used in both the first and the second memory transistor.
The first floating gate
54
and the second floating gate
55
are covered with an insulation film
60
, which is a so-called “ONO (i.e., Oxide-Nitride-Oxide)” laminated film constructed of, for example, a silicon oxide film, silicon nitride film and a silicon oxide film. Formed over both the first floating gate
54
and the second floating gate
55
through this insulation film
60
is a control gate
61
. In general, each of the first floating gate
54
, second floating gate
55
and the control gate
61
is made of polysilicon.
In the above-mentioned construction of the nonvolatile semiconductor memory device, as shown in
FIG. 30
, each of these regions
56
,
57
and
58
is constructed of a buried diffusion layer, and serves as a bit line covering a plurality of memory cells of the semiconductor memory device, wherein the memory cells are disposed adjacent to each other. On the other hand, as is clear from
FIG. 30
, the control gate
61
extends in a direction substantially perpendicular to a longitudinal direction of each of these bit lines
56
,
57
and
58
to serve as a word line. Next, with reference to each of
FIGS. 32A
,
32
B,
32
C,
33
A and
33
B, a method of manufacturing the conventional nonvolatile semiconductor memory device will be described in the order of its processing steps.
First, as shown in
FIG. 32A
, an oxidation-resistant mask film
63
constructed of a silicon nitride film is formed in an active region of a P-type semiconductor substrate
51
through a buffer film
62
of silicon oxide, and then subjected to an oxidation process which is well known as a so-called “LOCOS (i.e., Local Oxidation Silicon) process”, so that a device isolation oxide film
52
serving as a field oxide film is formed.
Then, both the buffer film
62
and the oxidation-resistant mask film
63
are removed. After that, as shown in
FIG. 32B
, a gate oxide film
53
is formed to cover the active region through a normal oxidation process. Then, by using a CVD (i.e., Chemical Vapor Deposition) process, a first conductive layer
64
made of polysilicon is formed on the entire surface of the semiconductor substrate
51
. Here, it will be understood that when a layer or film is referred to as being formed “on” another film or substrate, it can be directly on such another film or substrate, or intervening films may also be present therebetween. Subsequent to the above CVD process, as shown in
FIG. 32C
, a resist film
65
is formed by using a photolithography process to cover a region in which a floating gate for the first conductive layer
64
should be formed. Under such circumstances, the first conductive layer
64
is subjected to a patterning process, so that the first floating gate
54
and the second floating gate
55
both constructed of the first conductive layer
64
are formed side by side and spaced apart from each other to extend in the same direction. In forming both the first floating gate
54
and the second floating gate
55
through the above-mentioned patterning process of the first conductive layer
64
, mask alignment steps in the photolithography process are performed with reference to the device isolation oxide film
52
having been already formed.
After that, an N-type impurity such as arsenic and like impurities is injected into the active region in self-align manner with the use of the first floating gate
54
and the second floating gate
55
both serving as masks. Then, as shown in
FIG. 33A
, the first floating gate
54
and the second floating gate
55
thus formed are subjected to a heat treatment, so that the N-type drain regions
56
,
57
and the N-type source region
58
are formed and used as the buried diffusion layers. When an oxidation process is conducted after completion of the above heat treatment, ox
Hisamune Yoshiaki
Nakata Hidetoshi
Booth Richard A.
NEC Electronics Corporation
Young & Thompson
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