Semiconductor package and package stack made thereof

Details Semiconductor package and package stack made thereof Semiconductor package and package stack made thereof

2003-09-12

2004-11-02

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S737000, C438S617000, C438S116000

Reexamination Certificate

active

06812567

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a package stack made thereof.
2. Description of the Prior Art
The electronic industry continues to seek products that are lighter, faster, smaller, multi-functional, more reliable and more cost-effective. In order to meet the requirement of the electronic industry, circuit chips should be more highly integrated.
However, increasing the density of integration of chips may be expensive and have technical limitations. Therefore, three-dimensional (3-D) type semiconductor packaging techniques have been developed and used. In general, package stacks made by stacking a plurality of packages and stacked chip packages made by stacking a plurality of chips in a package have been used.
Package stacks may be manufactured by stacking packages that have already passed the necessary tests for their functions. Therefore, the yields and reliability of these package stacks may be higher than those stacked chip packages manufactured by stacking a plurality of chips without being tested. However, the package stacks may be thicker as compared with stacked chip packages, because of the thickness of each individual stacked package.
SUMMARY OF THE INVENTION
Exemplary embodiments of the invention provide a thinner semiconductor package, and a package stack using the thinner semiconductor package.
Exemplary embodiments of the invention also provide a semiconductor package, a package stack, a method of manufacturing a semiconductor package, and a method of manufacturing a package stack where one or more ends of one or more bonding wires are bonded to pads, such as bonding pads and/or board pads, using wedge bonding.
Exemplary embodiments of the invention also provide a semiconductor package, a package stack, a method of manufacturing a semiconductor package, and a method of manufacturing a package stack where two or more of solder bump pads, solder bumps, and an encapsulation part are provided on the same side of a board. In other exemplary embodiments, there are one or more solder bump pads, solder bumps, and/or encapsulation parts. In other exemplary embodiments, the side of the board is a lower side.
Exemplary embodiments of the invention also provide a semiconductor package, a package stack, a method of manufacturing a semiconductor package, and a method of manufacturing a package stack where two or more of solder bump pads, solder bumps, and an encapsulation part are provided on the same side of a board and where one or more ends of one or more bonding wires are bonded to pads, such as bonding pads and/or board pads, using wedge bonding.
An exemplary embodiment of the invention provides a semiconductor package comprising a board, a plurality of solder bump pads, a plurality of board pads, a plurality of wiring patterns, a plurality of contact pads, at least one chip, a plurality of bonding wires, an encapsulation part and a plurality of solder bumps.
The board may have an aperture, and the semiconductor chip may be installed in the aperture. The solder bump pads and the board pads may be formed on the lower surface of the board, and the solder bump pads may be electrically connected to board pads using the wiring patterns. The bonding pads may be formed on the semiconductor chip, and electrically connected to the board pads using the bonding wires. In order to reduce the height of loop of the bonding wires, both ends of the bonding wires may be attached to the bonding pads and the board pads by a wedge bonding.
The semiconductor chip, the bonding pads and the bonding wires may be encapsulated for protection. The contact pads may be formed on the upper surface of the board, and electrically connected to the solder bump pads by via holes.
The encapsulation part generally extends below the lower surface of the board. The height of each solder bump may be greater than the distance that the encapsulation part extend below the lower surface of the board.
The board may be covered with a solder resist except for the regions over the solder bump pads, the contact pads and the board pads.
A package stack according to an exemplary embodiment of the invention may be made by stacking the packages described above.
In the package stack according to an exemplary embodiment of the invention, the solder bumps of an upper package of any two adjacent packages may be electrically connected to the contact pads of the lower package of the two adjacent packages respectively.


REFERENCES:
patent: 5173766 (1992-12-01), Long et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 6097087 (2000-08-01), Farnworth et al.
patent: 6555917 (2003-04-01), Heo
patent: 1019950014678 (1995-12-01), None
patent: 1019990243555 (1999-11-01), None

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