Non-volatile memory device with diffusion layer

Details Non-volatile memory device with diffusion layer Non-volatile memory device with diffusion layer

2002-12-26

2004-08-10

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C438S268000

Reexamination Certificate

active

06774433

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC § 119 to Korean Patent Application No. 2001-85990, filed on Dec. 27, 2001, which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a non-volatile memory device and a method of fabricating the same. More specifically, the present invention is directed to silicon-oxide-nitride-oxide-silicon (SONOS) memory device having a cell transistor for storing information in a stacked gate insulating layer and a method of fabricating the same.
2. Description of the Related Art
Non-volatile memory devices are typically classified as either floating gate type non-volatile memory devices such as a flash memory device or floating trap type non-volatile memory devices such as a SONOS memory device. The flash memory device stores charges (i.e., free carriers) in a floating gate, and the SONOS memory device stores charges in a trap that is spatially isolated in a charge storage layer.
When storing free carriers, a flash memory device may lose all charges stored in a floating gate due to a partial defect of a tunnel oxide layer. Therefore, the flash memory device needs a relatively thick tunnel oxide layer as compared to the SONOS memory device. As a thickness of the tunnel oxide layer is increased to enhance reliability, the memory device needs complex peripheral circuits based on a requirement for a high operating voltage. This requirement prevents a high integration state of devices from being achieved and increases power consumption.
On the other hand, a SONOS memory device may have a relatively thin tunnel oxide layer as compared to the flash memory device because charges are stored in a deep level trap. Therefore, a SONOS memory device is operable at low applied gate voltages of 5-10V.
A conventional NAND-type SONOS memory device constructs a cell array using an enhancement mode transistor whose threshold voltage has a positive value. Since the threshold voltage of the enhancement mode transistor has a positive value, a positive sense voltage must be applied to a gate electrode of the memory transistor when program/erase signals are sensed in a read operation. Accordingly, a circuit for generating the sense voltage is required. In a read operation, a positive sense voltage is applied to a gate of a selected cell and a positive read voltage is applied to gates of unselected cells, so that the NAND-type SONOS memory device turns on the selected cell. Because a threshold voltage of a transistor in a write state is above 5V, the read voltage should be higher than 7V. The unselected transistor in an erase state is soft-programmed by the high read voltage, causing the threshold voltage of the unselected transistor to be high as well.
BRIEF SUMMARY OF THE INVENTION
A purpose of the invention is to provide a NAND-type memory device and a method of fabricating the same.
Another purpose of the invention is to provide a NAND-type memory device having a depletion mode cell transistor and a method of fabricating the same.
Another purpose of the invention is to provide a NAND-type memory device which reduces a peripheral circuit area by eliminating a read voltage generation circuit and a method of fabricating the same.
Another purpose of the invention is to lower the read voltage required to prevent the soft-programming phenomenon caused by a read voltage of a NAND-type SONOS memory device.
In order to achieve these purposes, the invention provides a non-volatile memory device having a multi-layered charge storage layer and a method of fabricating the same. The non-volatile memory device includes a bitline area, a string selection transistor, a plurality of memory transistors, a ground selection transistor, and a source area that are juxtaposed. Each of the memory transistors has a wordline, a multi-layered charge storage layer, and junction areas. The wordline crosses a predetermined area of a substrate of a first conductive type. The multi-layered charge storage layer is interposed between the wordline and the substrate. The junction areas are formed in the substrate, adjacent to opposite sides of the wordline, and are of a second conductive type. The memory transistors are depletion mode transistors with negative threshold voltages. There is a channel diffusion layer and an anti-punchthrough diffusion layer. The channel diffusion layer is formed at a surface of the substrate between the junction areas of the memory transistor, and the anti-punchthrough diffusion layer is formed between the junction areas below the channel diffusion layer. The channel diffusion layer and the anti-punchthrough diffusion layer are of the first conductive type. However, the concentration of the anti-punchthrough diffusion layer is higher than that of the substrate, and the concentration of the channel diffusion layer is lower than that of the substrate.
Similar to the memory transistors, the string selection transistor and the ground selection transistor are depletion mode transistors or enhancement mode transistors.
A method of erasing the non-volatile memory device includes the step of forming a diffusion layer of the first conductive type in a predetermined area of the first conductive type substrate. Impurities of the second conductive type are implanted into a predetermined area of the substrate where the first conductive type diffusion layer is formed, forming an inversely doped area at a surface of the first conductive type diffusion layer. A string selection gate, a plurality of wordlines, and a ground selection gate are formed to cross over a predetermined area of the first conductive type diffusion layer. Alternatively, the string selection gate and the ground selection gate may cross over the inversely doped area or cross over the first conductive type diffusion layer.


REFERENCES:
patent: 5471423 (1995-11-01), Iwasa
patent: 6107126 (2000-08-01), Wu
patent: 6452232 (2002-09-01), Adan
patent: 2003/0148583 (2003-08-01), Adachi et al.

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