Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-13
2004-11-09
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S500000, C257SE21558, C257SE21684, C257SE21689, C257SE27081
Reexamination Certificate
active
06815762
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for manufacturing a semiconductor integrated circuit device having MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and, more particularly, to a technique which is effective if applied to the manufacture of a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
2. Background of the Invention
The LSI, represented by a large capacity DRAM of recent years, has encountered a serious problem in that the high cost of manufacture has been raised by an increase in the number of manufacturing steps, as the manufacturing process becomes more complicated with increases in integration, speed and function. In accordance with this, the number of insulating films and conductive films deposited over a semiconductor substrate at a temperature of 700 to 900° C. has increased to make it difficult to achieve a high performance for the MISFETs by realizing a shallow junction. Moreover, the increase in the wiring resistance resulting from the miniaturization raises an obstruction to the speedup.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a technique capable of reducing the number of heat treatment steps in a process for manufacturing a semiconductor integrated circuit device having MISFETs.
Another object of the present invention is to provide a technique capable of simplifying the process for manufacturing a semiconductor integrated circuit device having MISFETs.
Another object of the present invention is to provide a technique capable of lowering the wiring resistance of a semiconductor integrated circuit device having MISFETs.
Another object of the present invention is to improve the manufacturing yield of a semiconductor integrated circuit device having DRAMs.
Another object of the present invention is to improve the electrical characteristics of a semiconductor integrated circuit device having DRAMs.
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representatives of the aspects of the invention, as disclosed herein, will be briefly described in the following.
By a process for manufacturing a semiconductor integrated circuit device of the present invention, all conductive films to be deposited over a semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after formation the MISFETs.
By a process for manufacturing a semiconductor integrated circuit device of the present invention, all conductive films to be deposited over a semiconductor substrate are made of a metal or its compound.
By a process for manufacturing a semiconductor integrated circuit device of the present invention, all insulating films to be deposited over a semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after formation the MISFETs.
By the present invention, there is provided a semiconductor integrated circuit device comprising:
(a) a semiconductor substrate having a major surface;
(b) a first semiconductor region formed in the major surface of said semiconductor substrate;
(c) a first insulating film formed over the major surface of said semiconductor substrate and having a first opening for exposing a portion of said first semiconductor region to the outside;
(d) a first conductor layer made of a polysilicon film formed in said first opening;
(e) a second insulating film positioned over said first insulating film and having a second opening for exposing a portion of said first conductor layer to the outside; and
(f) a second conductor layer formed in said second opening,
wherein a silicide layer is formed at the interface between said first conductor layer and said second conductor layer.
According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device comprising:
(a) the step of forming a first semiconductor region in the major surface of a semiconductor substrate;
(b) the step of depositing a first insulating film over the major surface of said semiconductor substrate;
(c) the step of forming a first opening in said first insulating film in such a way as to expose a portion of said first semiconductor region to the outside;
(d) the step of forming a first conductor layer made of a poly-silicon film selectively in said first opening;
(e) the step of forming a silicide film of a refractory metal layer selectively only over said first conductor layer by depositing said refractory metal film over said first conductor layer and said first insulating film and by subjecting the same to a heat treatment;
(f) the step of removing said refractory metal film over said first insulating film while leaving the silicide film of said refractory metal layer;
(g) the step of depositing a second insulating film over said first insulating film to form a second opening for exposing a portion of the silicide film of said refractory metal layer to the outside; and
(h) the step of forming a second conductor layer in said second opening.
REFERENCES:
patent: 3657029 (1972-04-01), Fuller
patent: 4859619 (1989-08-01), Wu et al.
patent: 4900695 (1990-02-01), Takahashi et al.
patent: 4954214 (1990-09-01), Ho
patent: 5116780 (1992-05-01), Samata et al.
patent: 5292681 (1994-03-01), Lee et al.
patent: 5378652 (1995-01-01), Samata et al.
patent: 5448512 (1995-09-01), Hachisuka et al.
patent: 5449634 (1995-09-01), Inoue
patent: 5519237 (1996-05-01), Itoh et al.
patent: 5587338 (1996-12-01), Tseng
patent: 5624864 (1997-04-01), Arita et al.
patent: 5717250 (1998-02-01), Schuele et al.
patent: 5726098 (1998-03-01), Tsuboi
patent: 5748521 (1998-05-01), Lee
patent: 5783471 (1998-07-01), Chu
patent: 5837591 (1998-11-01), Shimada et al.
patent: 5854127 (1998-12-01), Pan
patent: 5900661 (1999-05-01), Sato
patent: 5986299 (1999-11-01), Nakamura et al.
patent: 6004839 (1999-12-01), Hayashi et al.
patent: 6031288 (2000-02-01), Todorobaru et al.
patent: 6037216 (2000-03-01), Liu et al.
patent: 6090700 (2000-07-01), Tseng
patent: 6114199 (2000-09-01), Isobe et al.
patent: 19504994 (1995-08-01), None
patent: 9027596 (1997-01-01), None
patent: 9275193 (1997-10-01), None
Aoki Hideo
Asano Isamu
Kajigaya Kazuhiko
Kumauchi Takahiro
Tadaki Yoshitaka
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Niebling John F.
Pompey Ron
LandOfFree
Semiconductor integrated circuit device and process for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and process for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and process for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3354489