Split-gate flash with source/drain multi-sharing

Details Split-gate flash with source/drain multi-sharing Split-gate flash with source/drain multi-sharing

2002-01-04

2004-11-16

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S258000, C438S264000, C438S265000, C438S266000, C257S314000, C257S315000, C257S316000

Reexamination Certificate

active

06818512

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and in particular, to split-gate flash memory cells and to a method of forming high density flash memory arrays using the same.
(2) Description of the Related Art
Various techniques of forming memory cells have been used in the semiconductor manufacturing industry to increase the density of flash memory arrays. One such technique is to share the source and drain regions interchangeably between adjacent cells on the same word line of a split-gate flash memory. For example, in the dual split-gate (DSG) shown in
FIG. 1
a
, two floating gates of the cells (A) and (B) share the same source/drain(S/D). More specifically, and as seen more clearly in the cross-sectional view (
1
b
) of the same substrate (
10
), the memory cell is a triple polysilicon split-gate structure in which the floating gate (
30
) above gate-oxide (
20
) is polysilicon level
1
, control gate (
50
), separated from the floating gate by inter-gate oxide (
40
), is polysilicon level
2
, and the word select gate (
80
), separated from the control gate by nitride layer (
60
) is: polysilicon level
3
. It will be noted that third polysilicon (
80
) is isolated from both the floating gate and control gate by oxide spacer (
70
) as shown in the same Figure. Source/drain diffusions (
13
) are placed every two floating gates apart, thus improving density over the conventional cell, which has separated source and drain regions. Although two floating gates share the same word gate, source and drain regions, read and/or program to a single floating gate is possible because control gates are separated. Above each of the floating gates lies a control gate which controls the voltage of the individual floating gate by capacitance coupling. The control lines run parallel to the source/drain. Some of the disadvantages of the DSG cell are high program voltages of about 12V and also high voltages during read. A high control gate voltage of 12V is required during read operation when one of the floating gates is being accessed in order to mask out the effects from the other floating gate. Adjacent cells which may share the same diffusion or control gate voltages will be effectively disabled from the operation by suppressing the other floating gates with a very low ~0 control gate voltage. The same kind of over-ride and suppress techniques are used during program in order to target a single floating gate cell. In this way, program and read operations can be performed on the high density, self-aligned dual-bit split-gate flash/EEPROM cell.
As described more in detail by Y. Ma, et al., in U.S. Pat. No. 5,278,439 the DSG shown in
FIGS. 1
a
and
1
b
contains two bits, A and B, one in each cell. This can be better understood by considering
FIGS. 1
d
and
1
e
with the key shown in
FIG. 1
c
. (See also, Y. Ma paper on “A Dual-bit split-Gate EEPROM (DSG) Cell in Contactless Array for single-Vcc Height Density Flash Memories”). The cell has two floating gates, one control-gate (CG), one transfer-gate (TG), one common selected gate (SG), and the two bits share one pair of drain (D) and source (S). As shown in
FIG. 1
b
, the CG and TG are structurally identical. The SG channel is formed by a split-gate located between CG and TG. The dual-bit cell is accessed by five terminals, as shown in
FIGS. 1
d
and
1
e
. The conventions of the five active terminals are referred to as the left (
90
) or right (
95
) selected bit in the cell, as indicated in the same Figures. It will be apparent to those skilled in the art that in comparison with a conventional single-bit cell, the DSG's cell size savings comes directly from the shared and self-aligned SG. Of the three directly connected channels (CG, SG, and TG) between the source and drain, two work as a transfer channel (
17
), one as control-channel (
15
) for the selected channel, as shown in
FIG. 1
b
. During an address switch between the left and right bits in the cell, the CG and TG terminals exchange their functions, so do the terminals of drain and source. Within a cell, the two bits are reciprocally equal.
The various program (write), erase and read operations for a DSG are illustrated in
FIGS. 2
a
-
2
c
and
3
a
-
3
c
.
FIGS. 2
a
-
2
c
schematically represent the cross-sectional views of a DSG while
FIGS. 3
a
-
3
c
represent a top view of the same DSG where Figure numbers with the suffixes (a), (b) and (c) refer to the write, erase and read operations, respectively. The key shown in
FIG. 1
c
also apply to
FIGS. 2
a
-
2
c
and
3
a
-
3
c
so that the five terminals shown in
FIGS. 2
a
-
2
c
would be impressed with voltage (V) appropriate to the particular gate corresponding to each one of the operations.
Thus, keeping the same reference numerals in
FIGS. 1
a
-
1
e
referring to similar parts throughout the several views in
FIGS. 2
a
-
2
c
and
3
a
-
3
c
,
FIGS. 2
a
and
3
a
show the program or write operation for the same DSG as before. The write operation is performed bit by bit and the programmed bit is selected by a selected gate or word line (
80
) and bit line (
13
). In the write operation, source-side-injection mechanism is used where the selected gate (SG) is only weakly turned on so as to just turn on channel of unselected cell (
30
u
) while a higher voltage is used on control gate (CG) to provide higher vertical electric field to complete the write operation. In other words, hot-electrons (
12
W) are created at the transitional channel region (
17
) between SG and CG, and injected to the source side of the floating gate (
30
s
) while TG and CG are strongly turned on. The various voltage levels are shown for the program operation in both
FIGS. 2
a
and
3
a.
In the erase operation shown in
FIGS. 2
b
and
3
b
, negative-gate Fowler-Nordheim tunneling is used. Thus, during erase, with negative voltage of −10V on CG, an applied drain voltage of 7V pulls the stored electrons out of floating gate (
30
s
) via drain-side tunneling (
12
E), while the SG is grounded and the conduction channel cut off. As seen in
FIG. 3
b
, erased bits (
30
s
) are selected only by CG and a whole page of bits in the array are erased.
The read operation is accomplished by selecting the read bit by word line (
80
) and bit line (
13
) as in the write operation except that the TG and SG are fully turned on and the stored information is sensed by detecting whether the is channel current (
12
R) under the grounded CG.
In prior art there are other schemes for forming triple polysilicon flash EEPROM arrays with dual-bit capabilities. In U.S. Pat. Nos. 6,028,336 and 5,712,179 by Yuan, a triple polysilicon flash EEPROM array having a separate erase gate for each row of floating gates, and methods of manufacturing such an array are disclosed. As part of a flash EEPROM array on a semiconductor substrate, erase gates are formed in individual trenches between rows of floating gates. The erase gate is positioned along one sidewall of the trench in a manner to be capacitively coupled with the floating gates of one of the rows adjacent the trench but spaced apart from the floating gates of the other row adjacent the trench. In this way, a separate erase gate is provided for each row of floating gates without increasing the size of the array. The erasure of each row is then individually controlled. Two self-aligned methods of forming such an array are disclosed. One method involves forming a thick insulating layer along one sidewall of the trench and then filling a remaining space adjacent an opposite trench sidewall with polysilicon material forming an erase gate for the row of floating gates adjacent the other sidewall. A second method involves anisotropically etching a layer of polysilicon that is formed over the array in a manner to conform to the trench sidewalls, thereby separating the polysilicon layer into individual erase gates carried by the trench sidewalls.
In U.S. Pat. No. 6,13,098, a process for making and programming and operating a dual-b

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