Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2003-01-14
2004-06-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S685000, C438S301000
Reexamination Certificate
active
06746944
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fabrication of miniaturized high speed semiconductor devices, particularly to self-aligned silicide (salicide) technology. The present invention is particularly applicable to fabricating high speed miniaturized semiconductor devices with nickel silicide layers for reduced contact resistance.
BACKGROUND ART
As integrated circuit geometries continue to plunge into the deep submicron regime, it becomes increasingly more difficult to accurately form discreet devices on a semiconductor substrate exhibiting the requisite reliability and circuit operating speed. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the RxC product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross sections. Accordingly, continuing reduction in design rules into the deep submicron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
A common approach to reduce the resistivity of the interconnect to less than that exhibited by polysilicon alone, e.g., less than about 15-300 ohm/sq, comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface, since polycrystalline silicon is directly on the gate oxide.
Various metal silicides have been employed in salicide technology, such as titanium, tungsten, and cobalt. Nickel, however, offers particularly advantages vis-à-vis other metals in salicide technology. Nickel requires a lower thermal budget in that nickel silicide and can be formed in a single heating step at a relatively low temperature of about 250° C. to about 600° C. with an attendant reduction in consumption of silicon in the substrate, thereby enabling the formation of ultra-shallow source/drain junctions.
As miniaturization continues to plunge into the deep submicron regime, various issues arise in implementing salicide technology, including the formation of nickel silicide contacts. During silicidation, dopant deactivation occurs at the interface between the nickel silicide layers and silicon substrate. This reduction in dopant concentration is manifested by an increase in resistivity and, hence, contact resistance at the nickel silicide/silicon (NiSi/Si) interface.
Accordingly, there exists a need for salicide methodology enabling the formation of nickel silicide interconnection systems with reduced NiSi/Si contact resistance.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having nickel silicide contacts with reduced NiSi/Si interface contact resistance.
Additional advantages and other features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a gate electrode, having an upper surface and side surfaces, over a main surface of a silicon substrate with a gate dielectric layer therebetween; forming shallow source/drain extensions in the substrate; forming dielectric sidewall spacers on the side surfaces of the gate electrodes; forming preamorphized regions in the substrate at a first depth overlapping an interface between the silicon substrate and subsequently formed nickel silicide layers in the main surface of the silicon substrate; ion implanting impurities to form deep source/drain implants in the substrate at a second depth overlapping the preamorphized regions; laser thermal annealing to activate deep source/drain regions; and forming nickel silicide layers in the main surface of the substrate with the interface therebetween and forming a nickel silicide layer in the upper surface of the gate electrode.
Embodiments of the present invention include ion implanting to form the deep source/drain implants at a depth from the main surface of the substrate deeper than the preamorphized regions, as by forming the preamorphized regions at a depth of 200 Å to 400 Å and forming the deep source/drain implants at a depth of 800 Å to 1,500 Å. Upon laser thermal annealing, as by impinging a pulsed laser light beam at a radiant fluence of 0.2 to 0.8 joules/cm
2
for 1 to 10 nanoseconds, the dopant supersaturated preamorphized regions are crystallized at a high impurity concentration and the deep source/drain regions activated. Nickel silicidation is then implemented by depositing a layer of nickel and heating to form nickel silicide layers on the main surface of the silicon substrate and on the gate electrode.
Additional advantages of the present invention will be readily apparent to those skilled in the art from the following detailed description wherein the embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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Ogle Robert B.
Paton Eric N.
Tabery Cyrus E.
Xiang Qi
Yu Bin
Lindsay Jr. Walter L.
Niebling John F.
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