Register files and caches with digital sub-threshold leakage...

Details Register files and caches with digital sub-threshold leakage... Register files and caches with digital sub-threshold leakage...

2001-12-18

2004-02-10

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080

Reexamination Certificate

active

06690604

ABSTRACT:

FIELD
Embodiments of the present invention relate to digital circuits, and more particularly, to memory circuits such as caches or register files.
BACKGROUND
As transistors scale to smaller dimensions, sub-threshold leakage current may present circuit design challenges. In particular, for dynamic (domino) caches and register files, memory cells may contribute to sub-threshold leakage current. If such memory circuits are not designed properly, sub-threshold leakage current may cause a local bit line to be discharged when it shouldn't be, thereby leading to a possible error in a read operation.
For example,
FIG. 1
shows a portion of a cache or register file, where for simplicity only one local bit line is shown, and only one memory cell connected to the local bit line is shown. In practice, there usually are a plurality of local bit lines, where each local bit line usually has a plurality of memory cells sharing the local bit line. Memory cell
102
comprises cross-coupled inverters
104
, pass-access transistor (nMOSFET)
106
, and read-access transistor (nMOSFET)
108
. For simplicity, a write port is not shown. Memory cell
102
is connected to local bit line
110
.
The clock signal, denoted by &psgr;, is HIGH during an evaluation phase and LOW during a pre-charge phase. Pullup transistor (pMOSFET)
112
is ON during a pre-charge phase to ensure that local bit line
110
is at V
cc
before the next evaluation phase begins. A read operation occurs during an evaluation phase. During an evaluation phase, pullup transistor
112
is OFF and local bit line
110
is conditionally discharged LOW during a read operation, depending upon the data stored in the memory cell being read. For convenience, without loss of generality, we take the convention that a memory cell stores a logical “1” if it pulls its local bit line LOW during a read operation. Conversely, if a memory cell stores a logical “0”, then it does not actively pull its local bit line LOW during a read operation. For example, the gate of pass-access transistor
106
is HIGH (V
cc
) if memory cell
102
stores a logical “1”, and the gate is LOW (ground) if a logical “0” is stored.
The combination of inverter
114
and transistor (pMOSFET)
116
form a half-keeper. The half-keeper should be designed to maintain a local bit line in a charged state during an evaluation phase unless it is conditionally discharged during a read operation, where the condition depends upon the stored data. When a memory cell stores a logical “1”, there may be sub-threshold leakage current flowing through its read-access transistor. Consider a worst-case scenario in which memory cell
102
stores a logical “0” and each of the other memory cells (not shown) sharing local bit line
110
store a logical “1”. Then, during a read operation on memory cell
102
, the cumulative effect of the sub-threshold currents in the other memory cells may be sufficient to discharge local bit line
110
so that an incorrect read operation occurs, unless the half-keeper has sufficient strength to maintain local bit line
110
in its charged state.
To compensate for sub-threshold leakage current in the memory cells sharing a local bit line, the half-keeper is often increased in size, e.g., the effective ratio of the gate width to channel length is increased. However, increasing a half-keeper increases contention during a read operation when the stored data being read is a logical “1”, thereby possibly increasing the delay in a read operation.


REFERENCES:
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5880608 (1999-03-01), Mehta et al.
patent: 6600340 (2003-07-01), Krishnamurthy et al.

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