Non-volatile semiconductor memory device and manufacturing...

Details Non-volatile semiconductor memory device and manufacturing... Non-volatile semiconductor memory device and manufacturing...

2003-03-24

2004-11-16

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S424000

Reexamination Certificate

active

06818508

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device having memory cells based-on a stacked gate structure, and to a manufacturing method thereof.
What has hitherto been known as a non-volatile semiconductor memory (EEPROM (Electrically Erasable Programmable Read-Only Memory)) capable of electrically reprogramming data, is a flash memory using memory cells taking a MOS transistor structure based on a stacked structure of a charge-storage layer and a control gate.
FIG. 1
is a plan view showing a NOR type EEPROM using those memory cells.
FIGS. 2A and 2B
are sectional views taken along the lines A-A′ and B-B′, respectively, in FIG.
1
.
Isolation insulating films
102
are buried into a memory cell array area on a silicon substrate
101
, thereby defining device forming regions
103
continuous in a y-direction at a predetermined interval in an x-direction. Charge-storage layers
105
are provided via tunnel insulating films
104
on the substrate with the device being thus isolated, and a control gate
108
is provided via a gate-to-gate insulating film
107
on the charge-storage layers
105
, thus configuring a memory cell. The charge-storage layer
105
is isolated by the isolation insulating film
102
and thus gets independent for every memory cell. The control gate
108
is continuously provided in the x-direction and serves as a word line common to a plurality of memory cells. The control gate
108
and the charge-storage layers
105
are formed in pattern in self-alignment manner so that the side ends thereof are aligned in the y-direction. Then, the control gate
108
is provided with an n-type diffused layer
6
in self-alignment. The memory cell is covered with an inter-layer insulating film
109
, and bit lines
110
extending in the y-direction are arranged on the layer
109
.
An execution of a data reprogramming process of the EEPROM involves applying a high electric field to between the substrate and the charge-storage layer, to allow a tunnel current to flow through between the charge-storage layer and the substrate, thus modulating a stored charge quantity of the charge-storage layer. A threshold level of the memory cell becomes higher with a larger quantity of negative charge existing within the charge-storage layer, whereas lower with a larger quantity of positive charge existing therein. Accordingly, electron injection into the charge-storage layer raises the threshold level (which may be, e.g., a programming state). On the contrary, pulling out of the electrons from the charge-storage layer lowers the threshold level (which may be, e.g., a data erasing state).
The most important parameter for the data reprogramming of the memory cell described above is a ratio C
1
/C
2
of a capacitance C
1
between the charge-storage layer
105
and the substrate
101
to a capacitance C
2
between the control gate
108
and the charge-storage layer
105
. With the substrate set at an electric potential of 0, when a voltage Vcg is applied to the control gate
108
, a voltage Vfg of the charge-storage layer
105
is given such as Vfg=C
2
·Vcg/(C
1
+C
2
). Accordingly, a voltage applied to the tunnel insulating film
104
is determined by a coupling ratio K=C
2
/(C
1
+C
2
)=1/{1+(C
1
/C
2
)}.
A generation of a tunnel current requires applying an electric field as high as several tens of MV/cm to the tunnel insulating film. It is required for attaining this that the high voltage Vfg on the order of 10V be applied to between the charge-storage layer and the substrate. The charge-storage layer is coupled to the control gate by capacitance-coupling; hence a high voltage of approximately 20V is needed as the voltage Vcg=K·Vfg to be applied to the control gates. Even when the same voltage is applied to the control gates, if the coupling ratio K is different, the voltage applied to the tunnel insulating film becomes different, to attain different threshold levels for the memory cell. This causes an expansion of a threshold value distribution in the programming state of the memory cell. It is therefore of importance to uniformize the coupling ratio K.
FIG. 3
shows dimensions of the respective elements of the conventional memory cell structure. A capacitance ratio C
2
/C
1
is obtained by using these dimensions in the following formula:
C
2
/
C
1
={
Wa
+2(
d+Tsti
++Wing)}
Tox/Wa
·Tono
Wing=(Wsti−
SL
)/2
The capacitance C
2
is determined by a face-to-face area between the charge-storage layer
105
and the control gate
108
. Hence, variation in the capacitance C
2
is caused by variation in thickness of the charge-storage layer and variation in a length Wing (which is so-called a Wing length) of an overhang into the isolation region of the charge-storage layer
105
.
Further, there is a high possibility in which the thickness of the charge-storage layer
105
is not uniform as shown in
FIG. 3
when the device forming area and the isolation region have different heights. The non-uniformity of the thickness of the charge-storage layer leads to variation in an effective surface areal size of the charge-storage layer. This is also a factor for causing variation in the capacitance C
2
.
The wing length Wing is determined by an isolation width Wsti and a cut width (a so-called slit width) SL of the charge-storage layer. Cell miniaturization in order to increase the capacity of the EEPROM and decrease the cost thereof, often results in the dimensions of the isolation width Wsti and the slit width SL becoming the minimum width among those decided when the memory cells have been manufactured. In the memory cell described previously, the slit width SL of the charge-storage layer
105
is smaller than the isolation width Wsti and is therefore the minimum dimension. The isolation width in combination with the device forming area, however, determines a pitch of the bit lines, and it is therefore desired that the isolation width Wsti be set small to the greatest possible degree in order to shrink the memory cell array area.
A method utilizing the side-wall remaining technique has already been proposed by the present inventors (K. Shimizu et al. '97IEDM) for achieving a small slit width falling within the range of the small isolation width and smaller than this isolation width. According to this method, the masking material for slit processing is formed in pattern on the charge-storage layer, and thereafter an additional masking material is deposited with the side wall remaining, thereby obtaining a small slit width.
FIGS. 4A
to
4
E show the memory cell manufacturing process described above.
As shown in
FIG. 4A
, gate material layers
105
a
are deposited on a silicon substrate
101
through a gate insulating film
104
, and masking materials
201
are provided on the layers
105
a
, thus making a pattern formation so that the gate material layers
105
a
are left on the device forming area. Then, as illustrated in
FIG. 4B
, isolation trenches are formed by etching the substrate
101
by use of the masking materials
201
, and the isolation insulating films
102
are embedded into these trenches. Subsequently, as shown in
FIG. 4C
, the gate material layers
105
a
are deposited again, and masking materials
202
for slit processing are formed in pattern on the isolation insulating films
102
.
Further, as shown in
FIG. 4D
, masking materials
203
are deposited thin and left on only side walls of the masking materials
202
by anisotropic dry etching. A slit-processing window smaller than the minimum processing dimension is thereby formed. Then, gate material layers
105
b
are etched by using the masking materials
202
and
203
, whereby the charge-storage layer
105
taking the stacked structure of the gate material layers
105
a
and
105
b
is isolated by the isolation insulating films
102
and thus formed in pattern. Thereafter, as shown in
FIG. 4E
, a control gate
108
is provided via the inter-gate insulati

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