Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-05
2004-06-29
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S253000
Reexamination Certificate
active
06756260
ABSTRACT:
BACKGROUND
1. Technical Field
Methods for manufacturing semiconductor devices, and more particularly, methods for manufacturing semiconductor devices are disclosed which comprise a capacitor having a stable platinum (Pt) lower electrode formed using electrochemical deposition (ECD) process wherein an aluminum oxide (Al
2
O
3
) layer is formed on the seed conductive layer as an etching barrier film to prevent the seed conductive layer from being damaged during an etching process for patterning a dummy oxide layer.
2. Description of the Related Art
Generally, a method for increasing an area of a pole plate or a method of using a high dielectric constant material are used to increase capacitance of a capacitor.
When high dielectric constant materials are used, Pt is used as a pole material.
FIGS. 1
a
through
1
e
are cross-sectional diagrams illustrating sequential steps of a conventional method for manufacturing a DRAM capacitor using Pt.
Referring to
FIG. 1
a
, an interlayer insulating film
13
and a nitride film
14
are sequentially formed on a semiconductor substrate
11
, and etched according to a photo-etching process using a lower electrode contact mask to form a storage electrode contact hole (not shown) exposing a predetermined region of the semiconductor substrate
11
.
Thereafter, a polysilicon layer
15
is formed to fill the storage electrode contact hole and then over-etched to partially remove the top portion of the contact hole.
A titanium (Ti) layer (not shown) is formed over the resultant structure and thermally treated to form a titanium silicide (TiSi
2
) layer
17
.
The residual Ti layer is removed from the top portion of the interlayer insulating film
13
and then a titanium nitride (TiN) layer
19
is formed over the resultant structure and etched to form a contact plug
20
having a stacked structure. A seed Pt layer
21
is then formed over the resultant structure.
Referring to
FIG. 1
b
, a TiN layer (not shown) which is a diffusion barrier film and a dummy oxide layer (not shown) which is an insulating layer are sequentially formed on the seed Pt layer
21
.
The TiN layer and the dummy oxide layer are etched according to a photomask process and a dry etching process to form a sacrificial film pattern
29
which is a stacked structure of a TiN layer pattern
25
and a dummy oxide layer pattern
27
having an opening
30
.
Referring to
FIG. 1
c
, a lower electrode
31
is formed with a Pt layer filling the opening
30
using ECD process.
Referring to
FIG. 1
d
, the dummy oxide layer pattern
27
and the TiN layer pattern
25
are removed to expose the seed Pt layer
21
.
Referring to
FIG. 1
e
, the exposed portion of the seed Pt layer
21
is removed, and a dielectric film
33
is formed on the entire surface of the resulting structure using chemical vapor deposition (CVD) process.
In order to improve crystallization of the dielectric film, a rapid thermal process (RTP) is performed over the resultant structure, and a Pt layer is deposited on the dielectric film
33
using CVD method to form an upper electrode
35
.
However, in the conventional method for manufacturing the capacitor, when the dummy oxide layer pattern is removed to form the lower electrode, the TiN layer is affected by an etching gas due to a low 20:1 etching selectivity ratio of the TiN layer which is the diffusion barrier film and the dummy oxide layer, resulting in the damage of the seed Pt layer
21
in the portion where the sacrificial film pattern is formed. The resulting damage is shown as reference numeral
28
in FIG.
2
.
As a result, it is difficult to perform a subsequent process for forming the lower electrode with the Pt layer using ECD process and the yield and reliability of the semiconductor device are adversely affected.
SUMMARY OF THE DISCLOSURE
Improved methods for manufacturing semiconductor devices are disclosed wherein a stable lower electrode is obtained using a process for forming a Pt layer via the ECD process by forming an adhesive layer as an etching barrier film having a high etching selectivity ratio to the dummy oxide layer on the seed Pt layer to prevent the seed Pt layer from being damaged during a patterning process of a dummy oxide layer.
One disclosed method comprises:
forming an interlayer insulating film having a contact hole on a semiconductor substrate;
forming a contact plug filling the contact hole;
forming a seed conductive layer over the resultant structure;
forming an adhesive layer on the seed conductive layer;
forming a dummy oxide layer on the adhesive layer;
sequentially etching the dummy oxide layer and the adhesive layer to a sacrificial film pattern having an opening which exposes a portion of the seed conductive layer on the contact plug;
forming a lower electrode filling the opening using electrochemical deposition process;
sequentially removing the sacrificial film pattern and the seed conductive layer using the lower electrode as a mask; and
sequentially forming a dielectric film and an upper electrode on the entire lower electrode.
The adhesive layer can obtain adhesion between the conductive layer and the dummy oxide layer.
It is preferable that the adhesive layer comprises an Al
2
O
3
layer having a thickness of 50 to 500 Å using CVD process, reactive sputtering process or atomic layer deposition process.
In addition, the dummy oxide layer is removed using the dry etching process. Since the adhesive layer and the dummy oxide layer have an etching selectivity ratio of (adhesive layer: dummy oxide layer) about 50:1, it is used as an etch barrier film during the dummy oxide layer etching process for the lower electrode, thereby increasing an etching process window of the dummy oxide layer. Accordingly, the adhesive layer can achieve stability of the succeeding process for forming the lower electrode according to the ECD process using a Pt layer.
The adhesive layer is removed using the wet etching process. Here, the step of etching adhesive layer is performed in a solution having a HF to water ratio ranging from about 1:1 to about 1:1000 (wt %), preferably, about 1:1 to about 1:500 (wt %), or solution having HF to NH
4
F ratio ranging from about 1:7 to about 1:500 (wt %), preferably about 1:7 to about 1:200 (wt %).
The adhesive layer has a high wet etching rate over 10 Å/sec in diluted HF solution. Therefore, when removal of the dummy oxide layer is finished, a residual insulating layer can be removed within 10 seconds from a part where a storage node of the Pt layer is formed using a ECD process.
REFERENCES:
patent: 6383865 (2002-05-01), Hong et al.
patent: 6444479 (2002-09-01), Choi
patent: 6461913 (2002-10-01), Hong
patent: 2002/0013027 (2002-01-01), Hong et al.
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nguyen Thanh
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