Method for forming a conductive copper structure

Details Method for forming a conductive copper structure Method for forming a conductive copper structure

2003-01-22

2004-06-01

Gurley, Lynne (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S674000, C438S677000, C438S678000, C438S687000, C438S908000

Reexamination Certificate

active

06743719

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to manufacture of integrated circuits and more specifically to a method for forming an improved conductive interconnect structure.
BACKGROUND OF THE INVENTION
The push to sub-0.18 micron multilevel metallized interconnections, such as lines, via, and trenches, and the desire to produce faster semiconductor devices, has resulted in a shift toward the use of Copper for making electrical interconnections in ultra-large scale integration circuits. The deposition of Copper interconnects are not without difficulties, however. For example, when copper is etched, it tends to be redeposited elsewhere on the semiconductor device, or on the processing chamber. Copper atoms also readily diffuse into silicon-containing dielectric layers. The contamination by Copper in unwanted locations can degrade or destroy the performance of active devices in integrated circuits. One approach to reducing the problems with copper etching and diffusion, is the deposition of an underlying barrier layer to block the migration of Copper atoms into other components of the semiconductor. To facilitate the adhesion of copper to the diffusion barrier, a seed layer of copper is deposited over the diffusion barrier, followed by the deposition of a second thicker copper conducting layer over the copper seed layer.
Typically, the copper seed layer is deposited on a semiconductor wafer by a vacuum process, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The thick copper conducting layer is deposited by a wet process, such as electrochemical deposition (ECD) or electrode-less chemical deposition. Because the deposit of the seed layer and thick conducting layer involve two distinct processes and tools, the wafer has to be removed from the copper seed layer depositing tool, exposed to the atmosphere for a period, and then placed in the tool for depositing the thick layer. Backlogs and mismatches in the machine times for seed layer and thick layer deposition can extend the time window where the wafer is exposed to the atmosphere for several hours.
During this time window, the surface of the seed layer oxidizes. In addition, organic contaminants may form on the seed layer. The presence of an oxide layer on the copper seed layer can result in thinning or dissolution of the copper seed layer when placed in acidic electroplating solutions used for ECD. The resulting discontinuities in the seed layer exacerbate the formation of voids in the thick conducting layer during electroplating, thereby negatively impacting device performance and reliability. In addition, the oxide layer may not be fully removed during ECD. The continued presence of an oxide layer between the seed layer and the thick conducting layer weakens adhesion between these layers, making the interconnection more prone to mechanical failure. The current practice is to therefore minimize copper oxidation and organic compound contamination by restricting the period between depositing the seed layer and thick conducting layer by ECD processes. This approach, however may still result in unacceptably high oxidation and increased cycle times and therefore increased costs.
Previous approaches to mitigate copper oxidation and organic compound contamination are flawed, leading to degraded device performance. One approach, for example, is to produce thicker seed layers so that during electroplating, dissolution is not complete, and at least a portion of the copper seed layer remains. The problem with this approach is that for small openings, the thick seed layer can pinch off the trench opening resulting in center voids in the trench feature during the subsequent deposition of the thick conducting layer.
Another approach has been to deposit two seed layers in order to produce a thicker layer with better step coverage inside the trench or via feature. Typically the second seed layer covers the first seed layer and a native oxide layer that forms on the first seed layer. This particular approach, however, has the same problems as described above.
A third approach has been to chemically reduce the copper oxide layer back to elemental Copper in the presence of a Hydrogen gas plasma environment. But because reduction is performed in a separate tool when the wafer is taken out of the reduction tool, oxides formation on the seed layer surface can reoccur during the period when the wafer is waiting for thick Copper layer deposition by ECD. Moreover, there are additional costs and time to perform this reduction step.
A fourth approach has been to electrochemically reduce the copper oxide layer back to elemental copper in the presence of an electrical current. Although, this can be combined with the ECD process, it still requires an additional electrodeposition chamber for performing the electrochemical reduction, thereby resulting in additional processing steps and costs.
Accordingly, what is needed in the art is a method of making copper interconnections that do not exhibit the limitations of the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method forming a metal layer over a semiconductor wafer. The method includes exposing a copper oxide on a copper seed layer located over a semiconductor substrate, to a substantially copper-free reducing agent solution. The exposure is such that the copper oxide is substantially converted to elemental copper. The method further includes electrochemically depositing a second copper layer over the copper seed layer.
In another embodiment, the present invention provides a method of making an integrated circuit. The method includes forming active devices on a semiconductor substrate and forming interconnect metals lines on a dielectric layer located over the active devices. Forming interconnects on the interconnect metal lines includes exposing a copper oxide on a copper seed layer located over the semiconductor substrate to a substantially copper-free reducing agent solution, as discussed above. Forming interconnects on the interconnect metal lines further includes depositing, by using an electrochemical deposition tool, a second copper layer over the seed layer.
The foregoing has outlined preferred and alternative features of the present invention so that those of ordinary skill in the art better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purpose of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.


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