Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-09-06
2004-02-24
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060, C327S108000, C326S030000
Reexamination Certificate
active
06697286
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit for outputting transmit data the transmission line as a differential signal.
The present application claims priority of Japanese Patent Application No.2001-272778 filed on Sept. 7, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
In a trunk communications system or a like, for example, it is sometimes necessary to use a transmission line in order to interconnect functional blocks arranged separately from each other so that they can transfer data to each other.
In such a case, in order to output transmit data to the transmission line in a format of a differential signal, a driver circuit is used to match impedance of each of the blocks with that of the transmission line and also to set a signal level at a predetermined value.
FIG. 5
shows an example of the configuration of a conventional driver circuit
100
, which is disclosed in Japanese Patent Application Laid-open No. 2000-22516.
As shown in
FIG. 5
, the conventional driver circuit
100
includes P-type MOS (Metal Oxide Semiconductor) (hereinafter referred to as PMOS) transistors
101
A and
101
B, N-type MOS (hereinafter referred to as NMOS) transistors
102
A and
102
B, and resistors
103
to
107
.
In the driver circuit
100
shown in
FIG. 5
, the PMOS transistor
101
A, the resistors
103
and
104
, and the NMOS transistor
102
A and the PMOS transistor
101
B, the resistors
105
and
106
, and the NMOS transistor
102
B are connected in series between a power supply VDD and a ground (GND) respectively in such a configuration that the resistor
107
is connected between a midpoint between the resistor
103
and resistor
104
, and a midpoint between the resistor
105
and resistor
106
. Furthermore, the respective gates of the PMOS transistor
101
A and NMOS transistor
102
A are connected in parallel to an input terminal
109
and the respective gates of the PMOS transistor
101
B and NMOS transistor
102
B are connected in parallel to an input terminal
110
, while the midpoint between the resistor
103
and resistor
104
is connected to an output terminal
111
and the midpoint between the resistor
105
and resistor
106
is connected to an output terminal
112
.
In the driver circuit
100
of
FIG. 5
, the PMOS transistor
101
A, the resistors
103
and
104
, and the NMOS transistor
102
A make up a first push-pull circuit, while the PMOS transistor
101
B, the resistors
105
and
106
, and the NMOS transistor
102
B make up a second push-pull circuit.
In this configuration, suppose that transmit data including in-phase data is applied to the input terminal
109
of the first push-pull circuit and opposite-phase data obtained by inverting the transmit data is applied to the input terminal
110
of the second push-pull circuit.
When the in-phase data applied to the first input terminal
109
is LOW in level and the opposite-phase data applied to the second input terminal
110
is HIGH in level, only the PMOS transistor
101
A and NMOS transistor
102
B are turned ON, turning the PMOS transistor
101
B and NMOS transistor
102
A OFF. Furthermore, when the in-phase data input to the input terminal
109
is HIGH in level and the opposite-phase data applied to the input terminal
110
is LOW in level, only the PMOS transistor
101
B and NMOS transistor
102
A are turned ON, turning the PMOS transistor
101
A and NMOS transistor
102
B OFF.
Accordingly, at the output terminal
111
of the first push-pull circuit an opposite phase output signal with the transmit data occurs, while at the output terminal
112
of the second push-pull circuit an in-phase output signal with the transmit data occurs, so that the output signal including a differential signal synchronized with the transmit data with reference to an electric potential of a virtual midpoint C of the resistor
107
occurs between the output terminals
111
and
112
.
Supposing that the resistors
103
to
106
all have an equal resistance value Ra and the resistor
107
has a resistance value 2Rs and also that the input opposite phase data and input in-phase data have an amplitude large enough to permit the PMOS transistors
101
A,
101
B and NMOS transistors
102
A,
102
B to operate in their respective saturated regions always, then internal resistances of each of the transistors
101
A,
101
B,
102
A and
102
B in operating phase is negligibly small with respect to the resistance value Ra, so that differential output impedance between the output terminals
111
and
112
when the HIGH level is output is the same as that when the LOW level is output, thus leaving the output level as being dependent on a relative magnitude relationship between the resistance value Ra and resistance value Rs.
Furthermore, the output terminals
111
and
112
of the driver circuit
100
are connected to each one wire of a two-wire type of transmission line
120
(hereinafter may referred simply to as transmission line
120
), between ends of which resistors
121
and
122
are connected in series each having a resistance value RT, a midpoint of which is grounded through a capacitor
123
in an alternating-current operating phase, so that the two wires of the transmission line
120
are connected with the differential output impedance of the driver circuit
100
between the output terminals
111
and
112
on a transmission side and, on a reception side, connected with the respective resistors
121
and
122
and also to a reception circuit (not shown) having high input impedance.
Since the differential output impedance of the driver circuit
100
between the output terminals
111
and
112
is determined by a synthetic resistance value of a parallel connection of two kinds of resistors which is expressed by resistance values Ra and Rs, the resistor
107
can be used as an adjusting resistor so that the differential output impedance may be equal to characteristic impedance of the transmission line
120
and also that the resistance value RT may be equal to the characteristic impedance of the transmission line
120
, thus holding both the respective transmission side and the reception side of the transmission line
120
in a matched state.
Thus, in the driver circuit
100
, since the resistors (loads)
103
to
106
of the two push-pull circuits all have the same resistance value, the output impedance remains constant regardless of whether the differential output is HIGH or LOW in level, while a ratio between the resistance value Ra and resistance value RS can be changed to arbitrarily set an output amplitude to the transmission line
120
in a condition where the output impedance value is so held that the driver circuit
100
may be matched with the transmission line
120
.
It is thus possible, with the driver circuit
100
, to maintain a matched state with the transmission line
120
and also to decrease an output signal level of the transmission line
120
in order to prevent inductive interference against an external device (especially, other transmission lines), thus securing stable operations in a case where a number of transmission lines are established among the functional blocks.
According to the conventional driver circuit
100
shown in
FIG. 5
, in both the two push-pull circuits connected between the power supply VDD and the ground GND, the two resistors having the same resistance value are connected between the power-supply side PMOS transistor
101
A (
101
B) and the ground side NMOS transistor
102
A (
102
B) of each of these two push-pull circuits and have their midpoints each connected with a resistor in such a configuration that the two ends of this resistor are to be connected with the transmission line
120
and also that the gates of the PMOS and NMOS transistors of these two push-pull circuits are connected in parallel with each other to receive in-phase data and opposite-phase data respectively, so that it is possible to hold the output impedance constant regardless of whether the differential output is HIGH or L
Elms Richard
NEC Electronics Corporation
Nguyen Nam
Young & Thompson
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