Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-05-02
2004-08-03
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S093000, C326S094000
Reexamination Certificate
active
06772382
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the testing of integrated circuit chips and in particular the present invention relates to a driver circuit for use on an integrated circuit tester.
BACKGROUND
Integrated circuit chips or semiconductor devices typically undergo testing to verify their operability under a variety of conditions by their manufacturer. Generally, these chips are tested by automatic test equipment called an integrated circuit tester. The integrated circuit tester can be referred to as a “tester.” Chips are tested for a variety of reasons. For example, the tester may be used for sorting out faulty chips or for grading the chips on performance characteristics. In addition, a tester may be used during manufacture to guide the repair of chips that are defective. A chip that is being tested is commonly referred to as a device under test (DUT).
Generally testers include a host computer that runs software for controlling various tests on the DUT. Moreover, traditional testers contain numerous “channels” or “pins.” Each channel typically includes a driver circuit to generate test signals and/or a detector circuit or comparator circuit to measure output signals. To test a DUT, selected leads or ports on the DUT are coupled to selected channels of the tester. In a typical testing scenario, one or more of the channels is programmed to simulate an input to the chip. Moreover, a receiver in one or more channels is also programmed to detect one or more expected outputs.
Traditionally, single ended channels were used in the testers because single-ended signals were traditionally used in chips. A single-ended signal comprises a single signal for conveying a digital logic state with reference to a digital ground. A single-ended signal is detected as having a high logic level, a low logic level or a logic state between a high and a low logic level (a “between” state). Problems can arise with single-ended signals during high speed operations due to interference from ground bounce, noise and cross talk.
Some modern chips running at high speeds use differential circuits to generate differential signals to convey logic states. These chips employ differential signal ports. Differential signals convey a digital logic state as differences between two signals, neither one of which is ground. The effects of ground bounce, noise and cross talk are less on high speed systems incorporating differential signals than those systems incorporating single-ended signals. Typically, a differential amplifier is used to compare the differential margin of the signals in determining the logic level. There is a need in the art for a tester that effectively tests a DUT having differential signal ports.
The channel circuitry of testers can also be programmed to generate or check for an expected signal at a precise time. For example, most chips are clocked. That is, most integrated circuits have a clock input that changes states on a periodic basis. Generally, a chip latches a set of input signals at a set time in relation to a change in the clock signal. If valid data signals are not applied to the chip at the change in the clock signal, the chip will latch improper data.
Traditionally, a common clock was used for every chip inside an electronic system. Using a common clock allows each chip to produce its output and latch its input in association with other chips in the electronic system. However, problems can occur with the common clock system when signals move through one part of the electronic system at a different rate than other parts of the electronic system. The differences in time are sometimes called “skew.” When designing a system, the skew must be taken into account. Typically, the faster the electronic system, the more difficult it is to design to compensate for the skew.
More recently, a new clocking architecture has been used in systems that need to process many operations per second. This architecture is sometimes referred to as “source synchronous,” “clock forwarding” or “echo clocks.” In a source synchronous architecture, each chip in an electronic system that produces output signals (data signals) also produces an output clock signal (data clock signal). The data clock signal is fed to other chips in the electronic system along with the data signals. The other chip uses the data clock signal input to latch the input data signals. Because the data clock signal and the data signals travel over similar paths, there is less skew between the data signals and the data clock signal than between the data signals and the common clock. There is a need in the art for a tester that effectively tests DUT's having a source synchronous architecture.
For the reasons stated above and for the reasons stated below, which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a tester with a driver circuit that can effectively test DUT's having differential signal ports and a source synchronous architecture.
SUMMARY
The above-mentioned problems with testers and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a driver circuit is disclosed. The driver circuit comprises a timing circuit and a driver. The timing circuit has two or more inputs to receive data signals at a first frequency and at least one output. The timing circuit generates a control signal having a second higher frequency and outputs signals based on the data signals and the control signal such that the output signals are independent of the effects of timing skew and timing jitter of the data signals. The driver has at least one input coupled to the at least one output of the signal timing circuit to receive the output signals.
In another embodiment, a driver circuit for an integrated chip tester comprises a driver, a multiplexer and a timing logic circuit. The multiplexer has a plurality of data inputs for receiving test data signals. The multiplexer further has at least one control input and at least one output. The at least one output of the multiplexer is coupled to the driver. In addition, the timing logic circuit is coupled to the at least one control input of the multiplexer. The timing logic circuit controls the selection of the data inputs of the multiplexer such that an output signal of the multiplexer is independent of the effect of timing skew and timing jitter of the test data signals.
In another embodiment, a differential driver circuit for an integrated chip tester comprises a driver, a multiplexer and a timing logic circuit. The driver has a pair of inputs and a pair of outputs. The multiplexer has four inputs for receiving data signals, a pair of outputs coupled to the pair of inputs of the driver, a first selector input and a second selector input. The first and second selector inputs control the frequency in which data signals are coupled to the pair of outputs of the multiplexer. The timing logic circuit is coupled to the first and second selector inputs of the multiplexer to provide control signals. Moreover, the timing logic circuit uses a Gray code to provide a first control signal to the first selector input and a second control signal to the second selector input.
In another embodiment a test driver system comprises a memory, a data logic circuit, a multiplexer, a timing logic circuit and a driver. The memory is used to store program data. The data logic circuit is coupled to process the program data in the memory. The data logic circuit has a plurality of outputs to output a plurality of data signals. The multiplexer has an input for each output of the data logic circuit. Moreover, each input is coupled to receive an associated data signal from the data logic circuit. The multiplexer further has at least one output and at least one select input to selectively control when the data signals are coupled to the output. The timing logic circuit is coupled to the at least one select input. The timing logic circui
Loftsgaarden Scott C.
Schaber Scott D.
Dildine R. Stephen
Fogg and Associates LLC
Lundberg Scott V.
Teradyne, Inc.
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