Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-06
2004-06-29
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S549000, C438S981000
Reexamination Certificate
active
06756272
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory device. In particular, one with an improved writing/erasing speed and reliability of the memory cells. The present invention also relates to a method of manufacturing this non-volatile semiconductor memory device.
2. Prior Arts
For the conventional non-volatile semiconductor memory devices that can electrically write and erase data, there are demands for improved writing and erasing speeds. In order to respond to these, several types of non-volatile semiconductor memory devices, which are disclosed in Japanese Patent Application Laid-open Nos. Hei-1-211979, Hei-4-348081, Hei-6-69516, and Hei-6-283721, have been proposed, where the writing/erasing speed and the reliability of the memory cells is improved by changing the thickness of the oxide film.
FIGS. 1
a
to
1
d
and
FIGS. 2
a
to
2
c
are cross-sections showing the process steps of manufacturing the conventional non-volatile semiconductor memory device as disclosed in Japanese patent Application Laid-open No. Hei-6-283721. As shown in
FIG. 1
a,
device separators
102
are formed on a substrate
101
using a conventional method with the lithographic process. As shown in
FIG. 1
b,
a silicon oxide film
103
, from which tunnel oxide films will later be formed, is then deposited on top of the substrate
101
. As shown in
FIG. 1
c,
a polysilicon film
104
, from which floating gate electrodes
104
will later be formed, is then deposited. An ONO film
105
, made up of a silicon oxide film, a silicon nitride film, and a silicon oxide film, which are grown one by one, is then formed. The ONO layer
105
serves as a capacitor film located between a control electrode and the floating gate electrode
104
. As shown in
FIG. 1
d,
the ONO film
105
and polysilicon film
104
are both patterned by lithography using the resist mask
110
. Thereafter, doping with ions such as phosphorous or arsenic is performed, so as to form source regions
107
and drain regions
108
(see
FIGS. 2
a
to
2
c
). Next, as shown in
FIG. 2
a,
only the drain regions
108
are masked by a resist mask
106
, and the source regions
107
are then doped with ions. As a result, each source region
107
is changed into a high voltage-proof structure. Next, as shown in
FIG. 2
b,
the resist mask
106
is removed, and the top surfaces of the diffused regions and the sides of the floating gate electrodes
104
are then all oxidized. Next, as shown in
FIG. 2
c,
a polysilicon film
109
, from which control gates will later be formed, is deposited. Afterwards, the control gate electrodes
109
, capacitor films
105
, and floating gate electrodes
104
are patterned. Consequently, the non-volatile semiconductor memory device
100
is completed.
According to the conventional non-volatile semiconductor memory device, since the floating gate electrode is overlapped with the outer area of its corresponding drain region, the impurity concentration of most of the overlapped drain region is low, and an expansion of the depletion layer may easily occur. Since the voltage applied to the drain region is used to extend the depletion layer, the actual voltages applied to the tunnel oxide film is low. According to the conventional non-volatile semiconductor memories, there is a problem where the writing speed is low due to the fact that it is impossible to apply a high voltage to the tunnel oxide film between the floating gate electrode and drain region.
In the structure of the non-volatile semiconductor memory device
100
and the method of manufacturing the same as described above, in order to improve the hot electron holding capability and high voltage-proof capability when a writing or an erasing operation is performed, a thick gate oxide film is deposited on the overlapped region between each floating gate electrode
104
and its corresponding drain region
108
.
According to the conventional non-volatile semiconductor memories, however, there is a problem where the writing speed is low due to the fact that it is impossible to apply a high voltage to the tunnel oxide film between the floating gate electrode and drain region.
According to the conventional non-volatile semiconductor memories, besides, there is a problem with the poor reliability of the memory cells. That is to say, since the floating gate electrode is overlapped with the outer area of the drain region, holes are generated due to the tunnel effect that occurs between the energy bands. As a result, the memory cells may deteriorate, and have low reliability.
SUMMARY OF THE INVENTION
Accordingly, the present invention is provided taking the above problems into consideration. An objective of the present invention is to provide a non-volatile semiconductor memory device with an improved writing/erasing speed and improved reliability of the memory cells. Another objective of the present invention is to provide a method of manufacturing this memory device.
To attain the above objective, according to an aspect of the present invention, a non-volatile semiconductor memory device is provided, comprising a first insulating film(
15
), which is sandwiched between part of a drain region (
5
) and part of a floating gate (
24
), and which is located far away from the depletion layer between the said drain region (
5
) and a channel region (
23
), and a second insulating film (
14
), which is also sandwiched between the other part of the said drain region (
5
) and another part of the said floating gate (
23
), and which is thicker than the first insulating film (
15
). An example of the non-volatile semiconductor memory device is illustrated in FIG.
3
. The above reference numerals put in the parentheses are attached to respective corresponding elements in FIG.
3
.
According to an aspect of the present invention, a non-volatile semiconductor memory device is provided, comprising a first and second a memory cell which is located next to the said first memory cell, where the said first and the second memory cell share a source region; wherein, each of the said first and the said second memory cell are comprised of: a first insulating film(
15
), which is sandwiched between a part of a drain region (
5
) and a part of a floating gate (
24
), and which is located far away from the depletion layer between the said drain region (
5
) and a channel region (
23
); and a second insulating film (
14
), which is also sandwiched between the other part of the said drain region (
5
) and another part of the said floating gate (
23
), and which is thicker than the first insulating film (
15
). An example of the non-volatile semiconductor memory device is illustrated in FIG.
3
. The above reference numerals put in the parentheses are attached to respective corresponding elements in FIG.
3
.
According to an aspect of the present invention, a method of manufacturing a non-volatile semiconductor memory device is provided, comprising: a depositing step of depositing a first insulating film (
14
) on top of a drain region; a removing step of removing a part of the said first insulating film deposited (
14
), where the part is located far away from its corresponding depletion layer; and an oxidizing step of oxidizing the surface area of the said part, so as to form a second insulating film (
15
), which is thinner than the said first insulating film (
14
). An example of the above method is illustrated in
FIGS. 5
a
to
5
i.
The above reference numerals put in the parentheses are attached to respective corresponding elements in
FIGS. 5
a
to
5
i.
REFERENCES:
patent: 4833096 (1989-05-01), Huang et al.
patent: 5210048 (1993-05-01), Shoji et al.
patent: 5404037 (1995-04-01), Manley
patent: 5859453 (1999-01-01), Ahn
patent: 60-110163 (1985-06-01), None
patent: 61-174774 (1986-08-01), None
patent: 63-283070 (1988-11-01), None
patent: 63-306671 (1988-12-01), None
patent: 1-211979 (1989-08-01), None
patent: 2-37778 (1990-02-01), None
patent: 02-174171 (1990-07-01), None
patent: 3-46375 (1991-02-01), None
pate
Chaudhari Chandra
NEC Corporation
Scully Scott Murphy & Presser
LandOfFree
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