Integrated circuit with vertical transistors

Details Integrated circuit with vertical transistors Integrated circuit with vertical transistors

2001-05-29

2004-06-15

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S156000, C438S173000, C438S192000, C438S206000, C438S212000, C438S268000

Reexamination Certificate

active

06750095

ABSTRACT:

FIELD OF INVENTION
The invention relates to an integrated circuit arrangement with at least one transistor and to a method for its production.
BACKGROUND
For an integrated circuit arrangement, that is to say an electronic circuit which is integrated in a substrate, a high packing density is advantageous since, firstly, its switching speed is high because of short distances between its components and, secondly, its dimensions are low.
L. Risch et al, Vertical MOS Transistors with 70 nm channel length, ESSDERC (1995) 101, describes a transistor whose source/drain regions and channel region are arranged under one another. This so-called vertical transistor takes up less area than a conventional planar transistor whose source/drain regions and channel region are arranged beside one another and, consequently, can contribute to increasing the packing density of an integrated circuit arrangement. It is feared, however, that in the case of this transistor, floating-body effects occur, such as leakage currents on account of a parasitic bipolar transistor. In particular, at high frequencies, it is probable that the channel region will be electrically charged.
H. Takato et al, “High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs”, IEDM (1988) 222, describes a vertical transistor in which a lower source/drain region is not arranged directly under a channel region but underneath but offset laterally in relation to the former. The channel region is electrically connected to the substrate. In order to produce the transistor, a silicon island is etched into a substrate. A gate dielectric and a spacer-like gate electrode, which surrounds the silicon island at the side, are then produced. By means of implantation, the upper source/drain region is produced in an upper part of the silicon island, and the lower source/drain region is produced outside and laterally adjacent to the silicon island. The channel region is arranged in the silicon island, underneath the upper source/drain region. Consequently, the channel length is determined by the etching depth during the production of the silicon island.
German patent 195 19 160 C1 has proposed a DRAM cell arrangement in which each memory cell comprises a projection-like semiconductor structure which comprises a first source/drain region, a channel region arranged underneath, and a second source/drain region arranged under the latter, and which is surrounded annularly by a gate electrode. Semiconductor structures of memory cells are arranged in rows and columns. In order to produce word lines in a self-adjusting manner, that is to say without the use of masks which have to be adjusted, spacings between semiconductor structures arranged along the columns are smaller than spacings between semiconductor structures arranged along the rows. The word lines are produced by depositing and etching back conductive material in the form of gate electrodes adjoining one another along the columns.
SUMMARY
The invention is based on the object of specifying an integrated circuit arrangement having at least one transistor in which floating-body effects in the transistor can be avoided and which, at the same time, can be produced with an increased packing density and process accuracy in comparison with the prior art. In addition, a method of producing such a circuit arrangement is specified.
The problem is solved by an integrated circuit arrangement having at least one vertical MOS transistor, for which a substrate is provided which, in a layer adjacent to a surface of the substrate, is doped with a first conductivity type. Arranged on the substrate is a structured sequence of layers having a lower layer, a central layer doped with the first conductivity type and an upper layer. The sequence of layers has at least one first lateral and a second lateral face, which are each formed by the lower layer, the central layer and the upper layer. The lower layer can be used as a first source/drain region of the transistor, the central layer can be used as a channel region of the transistor, and the upper layer can be used as a second source/drain region of the transistor. In order to connect the channel region electrically to the substrate, a connecting structure doped with the first conductivity type is arranged on at least the first face of the sequence of layers in such a way that it laterally adjoins at least the central layer and the lower layer and reaches into the substrate. A gate dielectric adjoins at least the second face of the sequence of layers, and a gate electrode of the transistor adjoins the gate dielectric.
The problem is further solved by a method of producing an integrated circuit arrangement having at least one vertical MOS transistor in which, in order to form a sequence of layers on a substrate which is doped with a first conductivity type in a layer adjacent to a surface of the substrate, firstly a lower doped layer is produced, which can be used as a first source/drain region of the transistor, above this a central layer doped with the first conductivity type is produced, which can be used as the channel region of the transistor, and above that a doped upper layer is produced, which can be used as a second source/drain region of the transistor. In order to connect the channel region electrically to the substrate, a connecting structure doped with the first conductivity type is produced on a first face of the sequence of layers in such a way that it laterally adjoins at least the central layer and the lower layer and reaches into the substrate. The sequence of layers is structured in such a way that a second face of the sequence of layers is produced opposite the first face. A gate dielectric and, adjacent thereto, a gate electrode are produced at least on the second face of the sequence of layers.
The channel length of the transistor of the circuit arrangement is determined by the thickness of the central layer. As compared with the transistor according to H. Takato et al (see above), in which the channel length is determined by an etching depth, the channel length can be set more accurately. Consequently, the circuit arrangement can be produced with an increased process accuracy.
The connecting structure permits charge to flow away from the channel region, so that, as opposed to the transistor according to Risch et al (see above), floating-body effects are avoided. The channel region is not charged up electrically, even at high frequencies.
In order to avoid leakage currents, the connecting structure preferably consists of monocrystalline semiconductor material, such as silicon and/or germanium. The connecting structure is produced, for example, by epitaxy in a trench which cuts into or cuts through the sequence of layers. It is advantageous to provide a low dopant concentration, for example up to 3*10
17
cm
−3
, of the connecting structure, in order to keep capacitances between the substrate and the gate electrode small.
Alternatively, polycrystalline semiconductor material, such as polysilicon, can be used for the connecting structure. In this case, the trench is filled with the semiconductor material. Alternatively, the semiconductor material can be applied in a thickness which is not sufficient to fill the trench. The semiconductor material can then be etched back, so that the connecting structure is produced in the form of a spacer. If the connecting structure comprises polycrystalline material or material with a large number of defects, it is advantageous to provide a high dopant concentration of the connecting structure, for example 5*10
18
cm
−3
to 10
20
cm
−3
, in order to reduce the expansion of space charge zones into the connecting structure.
In order to increase breakdown voltages between the connecting structure and the source/drain regions and, at the same time, to prevent space charge zones reaching through, the scope of the invention includes increasing the dopant concentration of the connecting structures during their production, so that inner parts of the connecting structures ar

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