Sidewall coverage for copper damascene filling

Details Sidewall coverage for copper damascene filling Sidewall coverage for copper damascene filling

2001-11-20

2004-02-03

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C204S192120

Reexamination Certificate

active

06686280

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit manufacture with particular reference to techniques for filling small opening with metal, for example copper in a damascene structure.
BACKGROUND OF THE INVENTION
During the course of manufacturing an integrated circuit, the need frequently arises to fill an opening in the form of a hole or trench (generally in the surface of a dielectric layer) with material such as tungsten or copper. A particular example of this is the well-known damascene process in which conducting lines are formed that are flush with the surface rather than lying on top of it.
We illustrate, in
FIG. 1
, a particular problem which arises when a hole or trench needs to be filled with copper. This problem becomes increasingly more acute as the diameter or width of the opening gets to be less than about 0.3 microns. Before the opening can be filled using a high-volume technique such as electroplating, it is necessary to lay down a seed layer of copper. In
FIG. 1
we show a cross-section of a portion of dielectric (or some other material) layer
11
in which opening
15
has been formed. Layer
12
is a layer of field oxide that is normally present although not directly relevant to the practice on the present invention.
The problem mentioned above arises with the deposition of seed layer
13
(usually, but not necessarily) of copper. The most widely used processes for depositing the seed layer are vacuum evaporation and sputtering (known collectively as PVD or physical vapor deposition). Because of shadowing effects, there is a tendency for more material to build up near the mouth of the opening than lower down, giving the deposited seed layer the profile shown in FIG.
1
. In particular, there can be substantial overhang of the seed layer, as pointed to by arrows
14
, near the mouth of the opening.
When layer
13
is later built up, typically by electroplating, so as to fully fill opening
15
, material at the edges of the overhang come together before the hole can be fully filled, resulting in the trapping of a void within the copper plug (sometimes called the key hole effect).
An obvious approach to dealing with this problem is to reduce the amount of overhang to the point that void trapping does not occur. In the prior art this is done either by limiting the amount of copper deposited in the first place or by etching the seed layer back using conventional chemical means, such as wet or dry etching.
Simply reducing the thickness of the seed layer, while reducing the possibility of void formation, introduces a new problem which is illustrated in FIG.
2
. Shown there is seed layer
23
, having reduced thickness relative to seed layer
13
of FIG.
1
. However, if the overhang
24
is sufficiently reduced, bare spots such as
25
begin to appear on the side walls of the opening. The presence of such bare spots then has disastrous consequences for the subsequent hole filling procedure since multiple voids and poorly adherent areas get formed. The present invention shows how a seed layer having little or no overhang, while at the same time having sufficient thickness to fully cover the side walls, may be formed.
Effect on contact resistance between wiring layers
We note here that, because of the problems outlined above, it was necessary to limit trench depths so as to keep their aspect ratio (as seen in cross-section) to less than about 6:1, otherwise there was a danger of voids forming when they were filled with metal. This in turn meant that via holes extending downwards from the trench bottom to the next wiring level (i.e. dual damascene structures) had to be correspondingly deeper (i.e. their aspect ratio would typically be at least 6:1). As a result, the series resistance of the via (i.e. wiring level to wiring level contact resistance), when filled with metal, would be larger than desired. Typically, a contact resistance less than 1 ohm for a via size of 0.2 microns could occur. In
FIG. 6
we show a typical dual damascene structure of the prior art in which the depth of trench
61
is T
1
and the depth of via
62
is V
1
. It follows that any increase in the ratio T
1
/V
1
will reduce the wire-to-wire contact resistance.
A routine search of the prior art was conducted but no references were found that teach the solution described by the present invention. Several of these references were, however, of interest. For sample, Crank (U.S. Pat. No. 5,316,974) limits the seed layer to the bottom of the trench so that the filler plug grows (by electroplating) from the bottom up and not from the vertical sides, thereby avoiding void formation.
Zhao et al. (U.S. Pat. No. 5,674,787) form the seed layer by exposing the conductor at the bottom of the hole and then dipping it in a solution that deposits a thin copper layer by displacement. A plug is then grown on this seed layer using an electroless process.
Venkatraman (U.S. Pat. No. 5,677,244) dopes aluminum with copper by first laying down an agglomerated copper film, then depositing the aluminum copper then heating so as to diffuse the copper islands throughout the aluminum.
Venkatraman et al. (U.S. Pat. No. 5,814,557) describe a process for filling the trench/hole of a damascene structure by depositing two different conductors one after the other.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for filling a trench or hole at the surface of an integrated circuit without trapping voids or leaving bare spots on the side walls.
Another object of the invention has been to provide an apparatus in which to implement the process of the present invention.
A further object of the invention has been to provide a process for the formation of damascene wiring that is free of trapped voids (key hole effect).
A still further object of the invention has been that said process and apparatus be fully compatible with current techniques in use for the manufacture of semiconductor integrated circuits.
These objects have been achieved by first depositing a seed layer in the hole or trench by means of PVD, in the usual manner. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. It is in general preferable to perform the deposition and etching of the seed layer in the same apparatus without breaking vacuum between operations. When the sputter etch conditions specified by the invention are followed all overhang by the seed layer at the mouth of the trench or hole is essentially eliminated without the introduction of any poorly adhering or bare spots on the side walls.
This technique can be further improved by several refinements including multiple, sputter etching and seed layer deposition steps, increasing the T/V ratio discussed above, and using sputtering under varying conditions of pressure and voltage both to form the seed layer as well as to flatten it.


REFERENCES:
patent: 5316974 (1994-05-01), Crank
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5677244 (1997-10-01), Venkatraman
patent: 5814557 (1998-09-01), Venkatraman et al.
patent: 6177347 (2001-01-01), Liu et al.
patent: 6375810 (2002-04-01), Hong
patent: 2002/0110999 (2002-08-01), Lu et al.

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