Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2001-08-29
2004-08-17
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S308000, C438S482000, C438S487000, C438S517000, C438S798000
Reexamination Certificate
active
06777317
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor gate doping, and more particularly to a laser thermal processing method for gate doping in semiconductor devices.
2. Description of the Prior Art
Improvements in semiconductor technology and semiconductor manufacturing are the main drivers to the reduction of cost and the increase in speed of computers. There have been many improvements of semiconductor devices to increase their speed and performance, ranging from packaging of integrated circuits (“chips”) to the wiring of the devices on the chip, to the design of the devices themselves.
Another main driver in semiconductor technology is the trend toward smaller device structures. Metal oxide semiconductor field effect transistors (MOSFET) with submicron gate dimensions of the order of 100 to 250 nm are being developed. Performance improvements for these small gate dimension devices are generally obtained by changing the physical structure and materials used in the device and by inventing new processes or improving an existing process for making the devices.
For example, a method for doping of polycrystalline silicon gates includes a low energy ion implantation of a dopant followed by a thermal anneal for activation of the dopant. Examples of dopants used in polycrystalline silicon gates include boron, BF
2
+, arsenic and phosphorus, among others. Referring to
FIG. 1
, boron dopant profiles in silicon produced by conventional thermal annealing processes exhibit a gradual drop, spread out over a broad depth range. In the examples shown in
FIG. 1
this range is about 100 nm, which is comparable to the submicron gate dimensions of 100 to 250 nanometers.
The nature of the dopant profiles and the dopant concentration affect the performance of the chip. A junction with a gradual dopant profile is prone to sub-threshold leakage, while a reduced dopant concentration can result in a source or drain with a higher sheet resistance than is desired. The formation of abrupt junctions (e.g., sharp dopant profiles) reduces overlap capacitance and spreading resistance, and the ability to increase the dopant concentration lowers the sheet resistance. Both these effects serve to increase the speed and improve the performance of the chip.
Among the problems that occur with annealing of shallow polycrystalline silicon gates are gate depletion (i.e., low dopant concentration), inhomogeneous distribution and dopant diffusion through the thin insulating gate oxide (gate leakage). Gate depletion results when low annealing temperatures are used to avoid dopant diffusion through the thin insulating gate oxide. Low dopant concentration results in performance loss for the device. Full dopant activation and distribution is accomplished by high temperature annealing. However, the diffusion coefficient of dopants is higher along the grain boundaries than within the crystalline grains of the poly crystalline silicon gates resulting in inhomogeneous dopant distribution and dopant penetration through the insulating gate oxide which then leads in high leakage currents and poor device performance.
It is desirable to develop a thermal annealing process for doping and activating polycrystalline silicon gates that avoids gate depletion, leakage currents and results in improved device performance.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention provides a method of forming a doped polycrystalline silicon gate in a Metal Oxide Semiconductor (MOS) device formed on a top surface of a crystalline silicon substrate. The method includes forming first an insulation layer on the top surface of the silicon substrate and then an amorphous silicon layer on top of and in contact with the insulation layer. A dopant is then introduced in a top surface layer of the amorphous silicon and the top surface layer of the amorphous silicon is then irradiated with a radiation beam. The radiation beam heats the top surface layer of the amorphous silicon and causes melting and explosive recrystallization (XRC) of the amorphous silicon layer. The XRC transforms the amorphous silicon layer into a polycrystalline silicon gate and distributes the dopant uniformly throughout the polycrystalline gate.
Implementations of the invention may include one or more of the following features. The dopant may be introduced in the top layer of the amorphous silicon layer by ion implantation. The radiation beam may be a laser beam. The laser beam may be a pulsed laser having a wavelength of between 0.1 and 2.0 microns, a temporal pulse width of less than 1 ms, and an irradiance between 0.1 and 1000 J/cm
2
per pulse. The laser beam may have between 3 and 10 pulses at a repetition rate between 200 and 400 Hz. Following the XRC process a metal contact may be formed atop the polycrystalline gate. The metal contact may include at least one of tungsten, tungsten silicide, tungsten nitride, tantalum, tantalum nitride, titanium, titanium nitride and platinum. The insulation layer may include silicon dioxide. The dopant may include at least one of boron, BF
2
+, arsenic, and phosphorus. The polycrystalline gate may have a height of less than 500 nanometers.
In general, in another aspect, the invention features an alternative method of forming a doped polycrystalline silicon gate in a Metal Oxide Semiconductor (MOS) device formed on a top surface of a crystalline silicon substrate. The method includes forming first an insulation layer on the top surface of the silicon substrate and then an amorphous silicon layer on top of and in contact with the insulation layer. A dopant layer is then formed on top of and in contact with the amorphous silicon layer and the top surface layer of the amorphous silicon is then irradiated with a radiation beam. The radiation beam heats and melts the dopant layer and the top surface layer of the amorphous silicon and causes diffusion of the dopant in the top surface layer of the amorphous silicon layer and explosive recrystallization (XRC) of the amorphous silicon layer. The XRC transforms the amorphous silicon layer into a polycrystalline silicon gate and distributes the dopant uniformly throughout the polycrystalline gate.
Implementations of the invention may include one or more of the following features. The dopant may be deposited via sputtering, evaporation or chemical vapor deposition. The radiation beam may be a laser beam. The laser beam may be a pulsed laser having a wavelength of between 0.1 and 2.0 microns, a temporal pulse width of less than 1 ms, and an irradiance between 0.1 and 1000 J/cm
2
per pulse. The laser beam may have between 3 and 10 pulses at a repetition rate between 200 and 400 Hz. Following the XRC process a metal contact may be formed atop the polycrystalline gate. The metal contact may include at least one of tungsten, tungsten suicide, tungsten nitride, tantalum, tantalum nitride, titanium, titanium nitride and platinum. The insulation layer may include silicon dioxide. The dopant may include at least one of boron, BF
2
+, arsenic, phosphorus. The polycrystalline gate may have a height of less than 500 nanometers. The dopants may be incorporated at concentrations of 3×1020 ions/cm
3
, 5×10
20
ions/cm
3
and 1×10
21
ions/cm
3
for boron, arsenic and phosphorus, respectively.
Among the advantages of this invention may be one or more of the following. The small thermal budget and short process time utilized by the laser induced XRC process produces a fine microcrystalline grain structure in the silicon gate with evenly distributed dopants within the crystalline grains and the grain boundaries. The process is readily integrated into existing CMOS processing technology and improves device performance by producing polycrystalline silicon gates without gate depletion or gate leakage effects.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and description below. Other features, objects and advantages of the invention will be apparent from the following description
Seibel Cindy
Talwar Somit
Hogans David L.
Jones Allston L.
Jr. Carl Whitehead
Ultratech Stepper, Inc.
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