Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-29
2004-08-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06773984
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of depositing noble metals. The invention also pertains to methods of forming capacitor constructions, as well as to the capacitor constructions themselves.
BACKGROUND OF THE INVENTION
Capacitors are utilized in numerous semiconductor constructions, including, for example, dynamic random access memory (DRAM) devices. Capacitors comprise a pair of electrically conductive materials (frequently referred to as a storage node and a capacitor plate) which are separated from one another by dielectric material. The conductive materials are thus capacitively coupled with one another.
Various materials have been utilized for the conductive components of capacitor constructions, including, for example, metals, metal silicides, metal nitrides and conductively-doped semiconductor materials (such as, for example, conductively-doped silicon). Materials that can be particularly useful in capacitor constructions are so-called noble metals, which include, for example, platinum, rhodium, iridium, palladium and ruthenium. A difficulty in utilizing the noble metals is in patterning constructions from the metals. For instance, if platinum is utilized to form a conductive component of a capacitor construction, it can be difficult to pattern the platinum into a desired shape.
One of the methods that is frequently utilized for patterning platinum is chemical-mechanical polishing. However, such method can smear platinum. The smearing can cause undesirable defect structures.
It would be desirable to develop new methods of forming noble metals into desired shapes for semiconductor applications, and it would be particularly desirable if such new methods could be applied to fabrication of capacitor structures.
Although the invention was motivated by the applications discussed above, it is to be understood that the invention is not limited to such applications except to the extent that the applications are explicitly recited in the claims which follow.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of depositing at least one noble metal. A substrate is provided. The substrate includes first and second materials, with the first material being different than the second material. The first and second materials are exposed to a mixture comprising at least one precursor of at least one noble metal and at least one oxidant. During the exposure to the mixture, a layer containing at least one noble metal is selectively deposited onto the first material relative to the second material. In particular applications, the first material can comprise borophosphosilicate glass, and the second material can comprise either aluminum oxide or doped non-oxidized silicon.
In one aspect, the invention encompasses a method of forming a capacitor construction. A substrate is provided, and a first material is formed over the substrate. A second material is formed over the first material. Openings are formed to extend through the second material and into the first material. After the openings are formed, regions of the first and second materials are exposed to a mixture containing at least one precursor of at least one noble metal and at least one oxidant. A first layer comprising at least one noble metal is selectively deposited onto the first material relative to the second material as the materials are exposed to the mixture. The first layer is then exposed to conditions which roughen it. An electrically conductive second layer is formed over the roughened first layer, a dielectric third layer is formed over the second layer, and an electrically conductive fourth layer is formed over the third layer.
REFERENCES:
patent: 3653947 (1972-04-01), Kandler et al.
patent: 6518198 (2003-02-01), Klein
Gealy F. Daniel
Graettinger Thomas M.
Srividya Cancheepuram V.
Le Thao P.
Micro)n Technology, Inc.
Nelms David
Wells St. John P.S.
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