Method for planning layout for LSI pattern, method for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

Other Related Categories

C716S030000, C430S005000, C430S030000

Type

Reexamination Certificate

Status

active

Patent number

06691297

Description

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for planning a layout for an LSI pattern with optical proximity corrections ensured, a method for generating mask data and a method for forming an LSI pattern using these methods.
Recently, as a semiconductor large-scale integrated circuit (LSI) device has been downsized, a photolithographic step, which is one of the main process steps of an LSI fabrication process, has been affected by optical proximity effects more and more seriously. Specifically, a deviation of a feature size of a pattern actually transferred onto a resist from that of a mask pattern formed on a reticle has almost reached a non-negligible level. That is to say, if the feature size of an originally designed pattern is automatically applied to the mask pattern, then the size of the actually transferred pattern is likely to deviate from the originally designed one. This problem is particularly noticeable in a transistor, which plays a key role in determining the operability of an LSI. In this specification, a feature size of a pattern originally designed will be called a “designed size”, that of a pattern formed on a reticle or mask a “mask size” and that of a pattern actually transferred onto a resist an “actual size”, respectively.
Furthermore, every time an LSI of a new generation alternates with one of an older generation, the feature size of the LSI should be reduced discontinuously. For example, process technology of 0.18, &mgr;m generation has lately alternated with that of 0.25 &mgr;m generation. In this manner, a transistor feature size like the gate length thereof is usually reduced by about 70%. Whenever the gate length is reduced in this manner, one expects that the area of a cell implementing a circuit with the same function can also be reduced by about 50%, which is the square of 70%. This shrinkage rate is achievable by introducing a state-of-the-art exposure system using a radiation source with an even shorter wavelength or by improving the lithographic process itself.
These days, however, it has become more and more difficult to attain this shrinkage rate just by introducing a new system or improving the process. This is because the increase in deviation of an actual size from a mask size often prevents design rules, which are defined to ensure proper circuit operation, from achieving the 70% shrinkage rate. Examples of the design rules include the size of an extension of a gate and a contact margin.
FIG.
20
(
a
) illustrates an originally designed pattern
100
A and an actually transferred pattern
100
B of an ordinary field effect transistor (FET). As shown in FIG.
20
(
a
), the designed pattern
100
A includes a gate pattern
101
to be shaped into a gate layer and an active layer pattern
102
to be shaped into an active layer. In the actually transferred pattern
10
B, the width of the gate pattern
111
is smaller than its originally designed size, and both edge portions
111
a
of the gate pattern
111
no longer exist. If the portions of the gate pattern
111
overlapping with the active layer pattern
112
have been partially lost this way, then the transistor cannot operate normally.
To solve such a problem, extensions
101
a
are provided for both edges of the gate pattern
101
so as to extend from the active layer pattern
102
in the gate width direction as shown in FIG.
20
(
b
). As the size of a line pattern, which is called a “gate length
101
b
” decreases, the areas of the edge portions of the gate pattern
101
to be lost increase. In other words, the size
101
c
of the extensions
101
a
does not decrease proportionally to the gate length
101
b
. Accordingly, when the gate length
101
b
is to be reduced, the size
101
c
of the extensions
101
a
of the gate pattern
101
should be increased to ensure proper operation for the transistor. Thus, it has become more and more difficult for the design rule concerning the extension size
101
c
to achieve the 70% shrinkage rate.
In spite of the circumstances such as these, the design rule is still defined based on the deviation of an actual size from a mask size. For example, the design rule is defined by the 70% shrinkage rate compared to the previous generation. Thus, to reduce the total area of the circuit patterns, the design rule defined based on the 70% shrinkage rate is prioritized and applied to even a pattern that cannot satisfy the design rule completely, e.g., the extension size
101
c
of the gate pattern
101
.
Thereafter, a cell library is made up of a plurality of circuit patterns that have been designed in accordance with the design rule. LSI chip data is generated using the cell library to determine final conditions for the fabrication process. Based on these final process conditions, the deviation of an actual size from a mask size, which has been caused due to proximity effects, is estimated, thereby generating data for a mask layout that has been modified to eliminate the deviation of the actual size from the designed one. In this case, the actual sizes are estimated relative to the mask sizes using empirical models that reflect various conditions for estimating the actual sizes under predefined process conditions.
For example, in a portion of a circuit pattern where an actual size is thinner than its mask size, the mask size is thickened compared to the originally designed one. Conversely, in a portion of a circuit pattern where an actual size is thicker than its mask size, the mask size is thinned compared to the originally designed one. A mask pattern that is formed in view of optical proximity effects in this manner is called an “optical proximity corrected (OPC)” pattern.
According to the prior art method for generating LSI mask data, however, it is not until all the circuit patterns have been defined (i.e., while mask pattern data is being generated) that the OPC patterns are made. Thus, the OPC patterns could not be formed in some cases.
For example, consider a case shown in FIG.
20
(
a
) where the edges of the gate pattern
101
disappear. In such a situation, even if the mask size for the extensions
101
a
of the gate pattern
101
should be corrected to match its actual size with the size originally designed for the circuit pattern, the size
101
c
of the extensions
101
a
could not be changed. For instance, this size change is impermissible if the space between the extensions
101
a
and surrounding patterns thereof is of the required minimum size defined by the resolution limit.
Furthermore, the prior art method for generating mask data has various drawbacks including the following:
(1) A design rule defined without taking proximity effect corrections into account would result in an excessively increased mask size.
The proximity effects on the gate pattern can be compensated for by various techniques other than the extension of the extensions. For example, where gates are laid out with relatively wide space interposed therebetween, a hammerhead pattern may be added to each extension of a gate pattern that is not located over the active layer of a transistor. This hammerhead pattern does not extend the extension in the gate width direction, but expands only the edges of the extension in the gate longitudinal direction, thereby preventing the actual size of the gate pattern from shrinking too much at its edges in the gate width direction. In this manner, the proximity effect corrections can be made not only by compensating for the deviation of the actual size from the mask size but also by minimizing the deviation. Accordingly, if the size deviation was simply expected and a design rule was defined based on the result without estimating how much the deviation can be reduced by forming an OPC pattern, then the mask size determined would be unnecessarily large.
(2) In general, circuit patterns are made in accordance with a basic pattern placement rule and process conditions are defined to minimize a variation in sizes of patterns actually formed and a deviation of each actual size from its mask size. However, another patt

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