Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-08-20
2004-12-14
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S303000, C438S307000, C257S336000, C257S344000, C257S408000
Reexamination Certificate
active
06830978
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-240540, filed on Aug. 21, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device where an element and wiring are connected via a silicide film, and a manufacturing method for the same. Particularly, the present invention relates to a semiconductor device including a transistor operating at low voltage and a transistor driven at high voltage like flush memory, and relates to a manufacturing method for the same.
2. Description of the Prior Art
A semiconductor device such as flush memory is composed of low voltage transistors operating at low voltage of 5 V or lower and high voltage transistors operating at high voltage of about 20 V, which are mixedly mounted.
FIG. 1
is a sectional view showing a connecting portion of the high voltage transistor and wiring in a conventional semiconductor device. With reference to the
FIG. 1
, a manufacturing method for the conventional semiconductor device will be described.
First, a trench is formed at a predetermined position of a semiconductor substrate
10
. The trench is filled with an insulating material such as SiO
2
(silicon oxide) to form an element isolation film
11
. A surface of the semiconductor substrate
10
is then oxidized to form a gate insulation film (not shown). On the gate insulation film, a gate electrode
12
is formed in a predetermined pattern.
Thereafter, impurities are introduced into the surface of the semiconductor substrate
10
at comparatively low concentration using the gate electrode
12
as a mask to form a lightly doped drain (LDD) layers
13
. The LDD layer
13
is formed on both sides of the gate electrode
12
, but only one LDD layer
13
is shown in FIG.
1
.
Over the entire upper surface of the semiconductor substrate
10
, an insulation film such as SiO
2
is formed. The insulation film is anisotropically etched to be left only on both sides of the gate electrode
12
as sidewalls
14
.
Over the entire upper surface of the semiconductor substrate
10
, an insulating material such as SiO
2
is deposited to form an interlayer insulation film
15
. The gate electrode
12
, the LDD layer
13
, the element isolation film
11
and the like are covered with this interlayer insulation film
15
.
Subsequently, the interlayer insulation film
15
is selectively etched with photolithography to form a contact hole
15
h
reaching the LDD layer
13
. Then, impurities are ion-implanted at high concentration into the surface of the semiconductor substrate
10
through the contact hole
15
h
to form a source/drain layer
13
a.
The contact hole
15
h
is then filled with an electrical conductor such as metal to form a contact plug
15
a
. Subsequently, a metallic film is formed on the interlayer insulation film
15
and then patterned by photolithography to form wiring
16
.
In the semiconductor device manufactured in such a manner, a withstanding voltage of the transistor relates to a distance a between the source/drain layer
13
a
and the gate electrode
12
. The longer the distance a is, the higher the withstanding voltage of the transistor is.
In recent years, miniaturization of the semiconductor devices tends to be further accelerated. Along with the miniaturization, the area of a contact portion between the wiring and any one of the gate electrode and the source/drain layer has been reduced. Accordingly, in order to further improve properties of the contact portion, a silicide film formed by a salicide process has become used.
FIG. 2
is a sectional view showing another example of the conventional semiconductor device. With reference to
FIG. 2
, a conventional method of manufacturing a semiconductor device including the salicide process will be described.
First, impurities are ion-implanted at high concentration into an element isolation region of the semiconductor substrate
20
to form an impurity region
21
for element isolation. A surface of the semiconductor substrate
20
in the element isolation region is oxidized to form an element isolation film
22
.
The surface of the semiconductor substrate
20
in an element region is then oxidized to form a gate insulation film (not shown). On the gate insulation film, a gate electrode
23
is formed of polysilicon in a predetermined pattern. Subsequently, impurities are ion-implanted into the semiconductor substrate
20
at low concentration using the gate electrode
23
as a mask to form LDD layers
24
. The LDD layers
24
are formed on both sides of the gate electrode
23
.
Over the entire upper surface of the semiconductor substrate
20
, an SiN (silicon nitride) film
25
to be a silicide block is then formed and patterned in a predetermined shape. Impurities are then ion-implanted at high concentration into each LDD layer
24
through an opening of the SiN film
25
to form a source/drain layer
24
a
. Over the entire upper surface of the semiconductor substrate
20
, a metallic film such as cobalt or tungsten is formed and then heat-treated to form suicide films
26
a
and
26
b
on the surfaces of the gate electrode
23
and the source/drain layer
24
a
, respectively. Unreacted part of the metallic film is then removed by etching.
Subsequently, an insulation film such as SiO
2
is deposited on the entire upper surface of the semiconductor substrate
20
to form an interlayer insulation film
27
. In the interlayer insulation film
27
, a contact hole
27
h
reaching the source/drain layer
24
a
is formed and filled with a conductive material to form a contact plug
27
a.
A metallic film is then formed on the interlayer insulation film
27
and patterned by photolithography to form wiring
28
. In such a manner, the semiconductor device is completed.
However, the inventors consider that there is a problem shown below in the above described conventional method of manufacturing a semiconductor device.
In the semiconductor device shown in
FIG. 2
, the withstanding voltage of the transistor relates to a distance a between the gate electrode
23
and the source/drain layer
24
a
. On the other hand, when the contact hole
27
h
is formed in the interlayer insulation film
27
by photolithography, a margin b is necessary for mask alignment. The size of the silicide film
26
b
thereby needs to be larger than a size c of an end tip of the contact hole
27
h
. Accordingly, in the conventional method of manufacturing the semiconductor device, the transistor is increased in size by the margin b for mask alignment, that is, by the distance between an edge of the source/drain layer
24
a
and the contact plug
27
a
, thus limiting density improvement of the semiconductor device.
SUMMARY OF THE INVENTION
In the light of the above problem, an object of the present invention is to provide a semiconductor device including a silicide film on a gate electrode or a source/drain layer and allowing further density improvement compared with the conventional one, and a manufacturing method for the same.
The above subject is solved by a semiconductor device including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a low concentration impurity layer formed by introducing impurities at a low concentration into the semiconductor substrate on each side of the gate electrode; a first insulation film formed at least on the low concentration impurity layer; an opening provided in the first insulation film to expose part of the low concentration impurity layer; a source/drain layer formed by introducing impurities into the low concentration impurity layer at a position aligned with the opening at a concentration higher than that of the low concentration impurity layer; a silicide film formed by siliciding a surface of the source/drain layer; a second insulation film formed on the semiconductor substrate to cover the gate electrode and the first insulation film; a contact hole formed in a width larger
Ariyoshi Junichi
Torii Satoshi
Dang Trung
Westerman Hattori Daniels & Adrian LLP
LandOfFree
Semiconductor device and manufacturing method for the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method for the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method for the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3324145